Method and system for promoting scanning speed
In accordance with the present invention, a method and a system for promoting scanning speed are provided. The method comprises steps of determining a transmission rate of a transit interface, adjusting system clock responsive to the transmission rate of the transit interface to change a data generated rate, and scanning an original to generate data at the rate controlled by the system clock. The key aspect of the present invention is by adjusting system clock to change the data generated rate corresponding to the transmission rate of the transit interface. Therefore, in response to the transmission rate of the transit interface, the system clock is adjusted to produce the data at a rate that can reduce the possibility of memory buffer full leading to the reduction in the time wasting on start-stop processes and therefore promote the scanning speed without requiring the increase in size of a memory buffer.
1 .- 19 . (canceled)
20 . An apparatus, comprising:
means for adjusting a scanning system clock to adjust a data generation rate of a scanning system, based at least in part on said data transmission rate of a data interface; and
means for performing a scanning operation to generate scanning data at said adjusted data generation rate.
21 . The apparatus of claim 20 , further comprising means for transmitting said scanning data from said scanning system to a host device through said data interface.
22 . The apparatus of claim 20 , wherein said means for adjusting said data generation rate comprises means for reducing said data generation rate.
23 . An apparatus, comprising:
means for adjusting a scanning system clock based at least in part on a comparion of a data transmission rate of a data interface and a predetermined value; and
means for performing a scanning operation to generate scanning data at a rate controlled by said scanning system clock.
24 . The apparatus of claim 23 , further comprising means for transmitting said scanning data to a host device through said data interface.
25 . The apparatus of claim 23 , wherein means for adjusting said system clock comprises means for increasing a speed of said system clock to increase said controlled rate.
26 . The apparatus of claim 23 , wherein means for adjusting said system clock comprises means for reducing the speed of said system clock to reduce a data generation rate.
27 . An article comprising a storage medium, having stored thereon instructions that, when executed, result in:
adjusting a scanning system clock to adjust a data generation rate of a scanning system, based at least in part on a data transmission rate of a data interface; and
performing a scanning operation to generate scanning data at said adjusted data generation rate.
28 . The article of claim 27 , wherein said instructions, when executed, further result in:
transmitting said scanning data from said scanning system to a host device through said data interface.
29 . The article of claim 27 , wherein said data interface comprises a data interface selected from the group comprising: USB1.1, USB2.0, IEEE1394, EPP, and/or a SCSI.
30 . The article of claim 27 , wherein said instructions, when executed, further results in:
adjusting said data generation rate in response to a reduction in said data generation rate.
31 . The article of claim 27 , wherein said instructions, when executed, further result in:
adjusting said system clock by scaling a frequency generated by a clock generator by a scalar, wherein the scalar is based at least in part on said data transmission rate.
32 . The article of claim 31 , wherein said multiplier comprises a value selected from a plurality of predetermined values.
33 . An article comprising a storage medium, having stored thereon instructions that, when executed, result in:
adjusting a scanning system clock based at least in part on a comparison of a data transmission rate of a data inferrace with a predetermined value; and
performing a scanning operation to generate scanning data at a rate controlled by said scanning system clock.
34 . The article of claim 33 , wherein said instructions, when executed, further result in:
transmitting said scanning data to a host device through said data interface.
35 . The article of claim 33 , wherein said data interface comprises a data interface selected from the group comprising: USB1.1, USB2.0, IEEE1394, EPP, and/or a SCSI.
36 . The article of claim 33 , wherein said instructions, when executed, further result in:
adjusting said system clock by increasing the speed of said system clock to increase a data generation rate.
37 . The article of claim 33 , wherein said instructions, when executed, result in: adjusting said system clock by reducing the speed of said system clock to reduce a data generation rate.
38 . The article of claim 33 , wherein said instructions, when executed, further result in:
adjusting said system clock by multiplying a frequency generated by a clock generator by a multiplier, wherein the multiplier is based at least in part on said data transmission rate.
39 . A scanning system comprising:
a plurality of data interfaces to provide data between the scanning system and a host device, the plurality of data interfaces, said data interfaces being associated with respective data transmission rates;
circuitry to select one of the plurality of data interfaces to transmit data between the scanning system and a host device;
a system clock generator to generate an associated system clock responsive to said selection of one of the plurality of data interfaces; and
a scanning module to generate scanning data at a data generation rate controlled by said associated generated system clock.
40 . The system according to claim 39 , wherein said data interfaces comprises one or more data interfaces selected from the group comprising: USB1.1, USB2.0, IEEE1394, EPP, and/or a SCSI.
41 . The system according to claim 39 , wherein said system clock generator is adapted to generate said associated system clock in accordance with the data transmission rate of the selected data interface.
42 . The system according to claim 39 , wherein said system clock generator further comprises:
a clock generator to generate a frequency; and
a frequency multiplier to multiply said frequency by a plurality of multipliers to generate said corresponding system clock.