Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
View Patent ↗A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.
1. An electric circuit comprising:
a first clock buffer circuit receiving an external clock signal;
a first delay circuit for receiving an output of said first clock buffer circuit; and
a first clock timing control circuit, being supplied with an output of said first delay circuit, for generating a preceding internal clock before the output of said first clock buffer circuit being output; and
a first clock delivery circuit for receiving and outputting the preceding internal clock;
wherein said first delay circuit duplicates delay time characteristics of said first clock buffer circuit and said first clock delivery circuit.
2. An electric circuit as claimed in claim 1 , wherein the electric circuit multiplies a time difference between the external clock signal and the internal clock, which changes in response to the external clock signal, by a factor of N, where N is an integer equal to or larger than 2.
3. An electric circuit as claimed in claim 1 , wherein said first delay circuit includes a second delay circuit for duplicating delay time characteristics of said first clock delivery circuit, and a third delay circuit for duplicating delay time characteristics of said first clock buffer circuit.
4. An electric circuit comprising:
a first clock buffer circuit receiving an external clock signal;
a first delay circuit for receiving an output of said first clock buffer circuit;
a first clock timing control circuit, being supplied with an output of said first delay circuit, for generating a preceding internal clock before the output of said first clock buffer circuit being output;
a first clock delivery circuit for receiving and outputting the preceding internal clock;
a first optional circuit; and
a first output circuit for receiving the preceding internal clock and an output of said optional circuit, and outputting the output of said optional circuit in synchronization with the preceding internal clock;
wherein said first delay circuit duplicates delay time characteristics of said first clock buffer circuit and said first clock delivery circuit.
5. An electric circuit as claimed in claim 4 , wherein said electric circuit further comprises a first clock frequency control circuit for receiving an output of said clock buffer circuit, and an output of said first clock frequency control circuit is also supplied to said first clock timing control circuit.
6. An electric circuit as claimed in claim 4 , wherein said first clock timing control circuit stores capability information into a memory, and the capability information relates to the input from the output of said first clock buffer circuit and the output of said first delay circuit.
7. An electric circuit as claimed in claim 4 , wherein the electric circuit multiplies a time difference between the external clock signal and the internal clock, which changes in response to the external clock signal, by a factor of N, where N is an integer equal to or larger than 2.
8. An electric circuit as claimed in claim 4 , wherein said first delay circuit includes a second delay circuit for duplicating delay time characteristics of said first clock delivery circuit, and a third delay circuit for duplicating delay time characteristics of said first clock buffer circuit.
9. An electric circuit comprising:
a first clock buffer circuit receiving an external clock signal;
a first delay circuit for receiving an output of said first clock buffer circuit;
a first clock timing control circuit, being supplied with an output of said first delay circuit, for generating an output coincident with said external clock signal; and
a first clock delivery circuit for receiving and outputting the external clock signal;
wherein said first delay circuit duplicates delay tine characteristics of said first clock buffer circuit and said first clock delivery circuit.
10. An electric circuit as claimed in claim 9 , wherein the electric circuit multiplies a time difference between the external clock signal and the internal clock, which changes in response to the external clock signal, by a factor of N, where N is an integer, equal to or larger than 2.
11. An electric circuit as claimed in claim 9 , wherein said first delay circuit includes a second delay circuit for duplicating delay time characteristics of said first clock delivery circuit, and a third delay circuit for duplicating delay time characteristics of said first clock buffer circuit.
12. An electric circuit comprising:
a first clock buffer circuit receiving an external clock signal;
a first delay circuit for receiving an output of said first clock buffer circuit;
a first clock timing control circuit, being supplied with an output of said first delay circuit, for generating an output coincident wit said external clock signal;
a first clock delivery circuit for receiving and outputting the external clock signal;
a first optional circuit; and
a first output circuit for receiving the output coincident with the external clock signal and an output of said optional circuit, and outputting the output of said optional circuit in synchronization with the output coincident with the external clock signal;
wherein said first delay circuit duplicates delay time characteristics of said first clock buffer circuit and said first clock delivery circuit.
13. An electric circuit as claimed in claim 12 , wherein said electric circuit further comprises a first clock frequency control circuit for receiving an output of said clock buffer circuit, an output of said first clock frequency control circuit is also supplied to said first clock timing control circuit, and said first clock timing control circuit generates an output coincident with a part of said external clock signal.
14. An electric circuit as claimed in claim 12 , wherein said first clock timing control circuit stores capability information into a memory, the capability information relates to the input from the output of said first clock buffer circuit and the output of said first delay circuit, and said first clock timing control circuit generates an output coincident with a part of said external clock signal.
15. An electric circuit as claimed in claim 12 , wherein the electric circuit multiplies a time difference between the external clock signal and the internal clock, which changes in response to the external clock signal, by a factor of N, where N is an integer equal to or larger than 2.
16. An electric circuit as claimed in claim 12 , wherein said first delay circuit includes a second delay circuit for duplicating delay time characteristics of said first clock delivery circuit, and a third delay circuit for duplicating delay time characteristics of said first clock buffer circuit.