Flat panel display and method of manufacturing the same
View Patent ↗A flat panel display includes a substrate having a pixel region and a non-pixel region, the substrate having a transistor in the pixel region and a pad in the non-pixel region, a first planarizing layer in the pixel region covering the transistor and including a via hole exposing a portion of the transistor, and a second planarizing layer in the non-pixel region and having a pad contact hole opening the pad, the second planarizing layer being thinner than the first planarizing layer.
1. A flat panel display, comprising:
a substrate including a pixel region and a non-pixel region, the substrate having a transistor in the pixel region and a pad in the non-pixel region;
a first planarizing layer disposed in the pixel region covering the transistor and including a via hole exposing a portion of the transistor; and
a second planarizing layer in the non-pixel region and having a pad contact hole opening the pad,
the second planarizing layer being thinner than the first planarizing layer.
2. The flat panel display as claimed in claim 1 , wherein the second planarizing layer covers whole sides and an upper portion of the edge of the pad.
3. The flat panel display as claimed in claim 2 , wherein the second planarizing layer exposes a space between adjacent pads.
4. The flat panel display as claimed in claim 1 , wherein the second planarizing layer covers both sides and an upper portion of the edge of the pad.
5. The flat panel display as claimed in claim 4 , wherein the second planarizing layer exposes a space between adjacent pads.
6. The flat panel display as claimed in claim 1 , wherein the first and second planarizing layers are made of a same material.
7. The flat panel display as claimed in claim 6 , wherein the first and second planarizing layers are discontinuous.
8. The flat panel display as claimed in claim 1 , further comprising a light emitting element formed on the pixel region and connected to the transistor through the via hole.
9. The flat panel display as claimed in claim 8 , wherein the light emitting element comprises a first electrode, an organic light emitting layer and a second electrode stacked in that order.
10. The flat panel display as claimed in claim 1 , wherein the pad contacts conductive balls and a thickness of the second planarizing layer on the pad is smaller than a diameter of the conductive ball.
11. A method of manufacturing a flat panel display, comprising:
providing a substrate including a pixel region and a non-pixel region, the substrate having a transistor in the pixel region and a pad in the non-pixel region;
forming a planarizing layer on the pixel and non-pixel regions; and
patterning the planarizing layer to form a first planarizing layer in the pixel region and a second planarizing layer in the non-pixel region, the first planarizing layer having a via hole exposing a portion of the transistor, the second planarizing layer having a pad contact hole opening the pad and being thinner than the first planarizing layer.
12. The method as claimed in claim 11 , wherein the second planarizing layer covers whole sides and an upper portion of the edge of the pad.
13. The method as claimed in claim 12 , wherein the second planarizing layer exposes a space between adjacent pads.
14. The method as claimed in claim 11 , wherein the second planarizing layer covers both sides and an upper portion of the edge of the pad.
15. The method as claimed in claim 14 , wherein the second planarizing layer exposes a space between adjacent pads.
16. The method as claimed in claim 11 , wherein the planarizing layer is made of a photosensitive organic material.
17. The method as claimed in claim 16 , wherein the patterning of the planarizing layer comprises:
exposing the planarizing layer using a halftone photo mask as a photo mask; and
developing the exposed planarizing layer.
18. The method as claimed in claim 16 , wherein the patterning of the planarizing layer comprises:
exposing the planarizing layer using a first photo mask;
re-exposing the exposed planarizing layer using a second photo mask having different transmission regions from the first photo mask; and
developing the re-exposed planarizing layer.
19. The method as claimed in claim 11 , further comprising forming a light emitting element on the first planarizing layer, the light emitting element electrically connecting with the transistor through the via hole.
20. The method as claimed in claim 11 , wherein forming the light emitting element comprises stacking first electrode, an organic light emitting layer and a second electrode in that order on the first planarizing layer.