Thin film transistor substrate and method of manufacturing the same

1. A method of manufacturing a thin film transistor substrate, the method comprising:

providing a substrate wherein first and second semiconductor patterns are formed on a blocking layer;

forming a first gate insulating layer on the first and the second semiconductor patterns;

forming a first pattern of a second gate insulating layer overlapping with a channel region of the first semiconductor pattern,

forming a second pattern of the second gate insulating layer overlapping with a channel region of the second semiconductor pattern;

forming a first gate electrode overlapping with the channel region of the first semiconductor pattern;

forming a second gate electrode overlapping with the channel region of the second semiconductor pattern;

forming a first conductive type source/drain regions by injecting a high-concentration first conductive type impurity ion into the first semiconductor pattern; and

forming a second conductive type source/drain regions by injecting a high-concentration second conductive type impurity ion into the second semiconductor layer,

wherein the second conductive type impurity is injected into the blocking layer under the first semiconductor pattern when the second conductive type source/drain regions are formed.

2. The method of claim 1 , further comprising:

removing the first and second photoresist film patterns; and

forming low-concentration doping regions by injecting a low-concentration first conductive type impurity ion into the first semiconductor pattern.

3. The method of claim 1 , wherein the forming of the first and second patterns of the second gate insulating layer and the first and second gate electrodes comprises:

sequentially forming first and second gate insulating layers and a conductive layer on the blocking layer having thereon the first and second semiconductor patterns;

forming, on the conductive layer, a single-layered photoresist film pattern overlapping with the channel region and low-concentration doping regions of the first semiconductor pattern and having a first thickness, and a double-layered photoresist film pattern having a first thickness portion overlapping with the channel region of the second semiconductor pattern and second thickness portions overlapping with the source/drain regions of the second semiconductor layer;

forming the first gate electrode and a second gate pattern by patterning the conductive layer using the single-layered and double-layered photoresist film patterns as etching masks, and patterning the second gate insulating layer;

removing the second thickness portions of the double-layered photoresist film pattern; and

forming the second gate electrode by patterning the second gate pattern using as an etching mask the photoresist film pattern wherein the second thickness portions are removed.

4. The method of claim 3 , wherein the forming of the first and second patterns of the second gate insulating layer and the first and second gate electrodes further comprises forming first conductive type source/drain regions by injecting a high-concentration first conductive type impurity ion into the first semiconductor pattern using the single-layered and double-layered photoresist film patterns as etching masks, prior to removing the second thickness portions of the double-layered photoresist film pattern.

5. The method of claim 3 , further comprising forming first conductive type source/drain regions by injecting a high-concentration first conductive type impurity ion into the first semiconductor pattern using the first and second ion implantation mask structures as ion implantation masks before forming the second conductive type source/drain regions.

6. The method of claim 3 , further comprising forming first conductive type source/drain regions by injecting a high-concentration first conductive type impurity ion into the first semiconductor pattern using the first and second ion implantation mask structures as ion implantation masks after forming the second conductive type source/drain regions.

7. The method of claim 1 , wherein in the forming of the second conductive type source/drain regions, the peak doping concentration of the second conductive type impurity ion is present in the second semiconductor pattern.

8. The method of claim 3 , wherein the removing of the second thickness portions of the double-layered photoresist film pattern is performed using an ashing process.

9. The method of claim 1 , wherein the thickness of the second gate insulating layer is equal to or greater than the thickness of the first gate insulating layer.

10. The method of claim 1 , wherein the first conductive type is n-type and the second conductive type is p-type.

11. The method of claim 1 , wherein the first gate insulating layer comprises a silicon oxide film.

12. The method of claim 1 , wherein the second gate insulating layer comprises a silicon nitride film.

13. The method of claim 1 , wherein a boundary of the first conductive type source/drain regions substantially coincides with a boundary of the first pattern of the second gate insulating layer.

14. The method of claim 1 , wherein a boundary of the second conductive type source/drain regions substantially coincides with a boundary of the second gate electrode.

15. The method of claim 1 , further comprising:

forming low-concentration doping regions by injecting a low-concentration first conductive type impurity ion into the first semiconductor pattern,

wherein a boundary of the low-concentration doping regions substantially coincide with a boundary of the first gate electrode.