IP Library Granted Patent US 7,574,554
Granted Patent B2
US 7,574,554 · App. 11/503,050 · Granted Aug 11, 2009

Storage system and data protection method therefor

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Quick Facts
Patent No.
US 7,574,554
App. No.
11/503,050
Granted
Aug 11, 2009
Kind
B2
Abstract

To detect an address error in flash memory using a different data management unit from that in a hard disk drive. In cache memory, data read/written from/to a flash memory chip is managed in units of first data lengths. A page, which is the data management unit in a flash memory chip, includes a data section of a second data length from/to which a storage controller can read/write data; and a redundant section. When writing data, the storage controller creates a protection code enabling identification of a write destination page address, divides the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of a second data length, and writes the respective sets in a flash memory chip in units of second data lengths.

Claims (43)

1. A storage system comprising:

one or more flash memory modules each comprising one or more flash memory chips and a memory controller operable to control reading/writing of data from/to the flash memory chips; and

a storage controller comprising cache memory operable to temporarily store data read/written from/to one or more of the flash memory chips,

wherein,

in the cache memory, data read/written from/to the flash memory chips is managed in units of first data lengths;

in the flash memory modules, the data read/written from/to the flash memory chips is managed in page units;

the memory area of one page includes a memory area of a second length from/to which the storage controller can read/write data, and a memory area for a redundant section;

when writing data to a flash memory chip, the storage controller is operable to create a protection code enabling identification of address information for a write destination page;

divide the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of the second data length, and write the respective sets of the pieces of write data and protection codes in the flash memory chip in units of second data lengths; and

the storage controller is operable to compare the address information identified with the protection codes attached to the data read from the flash memory chip with the address information for the data that is intended to be read, and check whether or not there is an address error.

2. The storage system according to claim 1 , wherein the storage controller further includes a database storing relationships between the specifications of the flash memory modules and the second data lengths of the flash memory modules.

3. The storage system according to claim 1 ,

wherein the storage areas provided by flash memory modules are structured according to RAID; and

when an address error occurs in the data in any one of the flash memory modules, the storage controller is operable to rebuild the data having the address error in units of the second data lengths using the data stored in the other flash memory modules belonging to the same RAID group as the flash memory module storing the data having the address error; and overwrite the data having the address error with the rebuilt data.

4. The storage system according to claim 1 , the storage system further includes hard disk drives as storage media, wherein when an address error occurs in a hard disk drive, the storage controller is operable to overwrite/correct the data having the address error in units of the first data lengths.

5. The storage system according to claim 1 , wherein any one of the protection codes includes write-time information.

6. The storage system according to claim 1 , wherein any one of the protection codes includes an error detection code for protecting data of the second data length.

7. A storage system comprising:

one or more flash memory modules each comprising one or more flash memory chips and a memory controller operable to control reading/writing of data from/to the flash memory chips; and

a storage controller comprising cache memory that temporarily stores data read/written from/to one or more of the flash memory chips,

wherein,

in the cache memory, data read/written from/to the flash memory chips is managed in units of first data lengths;

in the flash memory modules, the data read/written from/to the flash memory chips is managed in page units;

the memory area of one page includes a memory area of a second length from/to which the storage controller is operable to read/write data, and a memory area for a redundant section;

the storage controller comprises a media identification unit that identifies the type of a storage medium connected thereto;

if a storage medium connected to the storage controller is a flash memory module, when writing data in a flash memory chip, the storage controller is operable to create a protection code enabling identification of address information for a write destination page; divide the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of the second data length, and write the respective sets of the pieces of the write data and protection code in the flash memory chip in units of second data lengths; and

the storage controller is further operable to compare the address information identified with the protection codes attached to the data read from the flash memory chip with the address information for the data that is intended to be read, and check whether or not there is an address error.

8. The storage system according to claim 7 , wherein the first data length is the sector length of a hard disk drive.

9. The storage system according to claim 7 , wherein data of the first data length includes data and a protection code enabling identification of address information of a write destination hard disk drive for that data.

10. The storage system according to claim 7 , wherein the storage controller further includes a database storing relationships between the specifications of the storage media and the second data lengths of the storage media.

11. The storage system according to claim 7 ,

wherein the storage areas provided by flash memory modules are structured according to RAID; and

when an address error occurs in the data in any one of the flash memory modules, the storage controller is operable to rebuild the data having the address error in units of the second data lengths using the data stored in the other flash memory modules belonging to the same RAID group as the flash memory module storing the data having the address error; and overwrites the data having the address error with the rebuilt data.

12. The storage system according to claim 7 , wherein, when an address error occurs in a hard disk drive, the storage controller is operable to overwrite/correct the data having the address error in units of the first data lengths.

13. The storage system according to claim 7 , wherein any one of the protection codes includes write-time information.

14. The storage system according to claim 7 , wherein any one of the protection codes includes an error detection code for protecting data of the second data length.

15. A data protection method performed in a storage system, the storage system comprising: one or more flash memory modules each comprising one or more flash memory chips and a memory controller that controls reading/writing of data from/to the flash memory chips; and a storage controller comprising cache memory operable to temporarily store data read/written from/to one or more of the flash memory chips, and the memory area of one page comprising: a memory area of a second length from/to which the storage controller can read/write data; and a memory area for a redundant section,

the method comprising:

managing the data read/written from/to a flash memory chip in units of first data lengths in the cache memory;

creating a protection code enabling identification of address information for a write destination page, when writing data in a flash memory chip;

dividing the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of the second data length;

writing the respective sets of the pieces of the write data and protection codes in the flash memory chip in units of second data lengths; and

comparing the address information identified with the protection codes attached to the data read from the flash memory chip with the address information for the data that is intended to be read and checking whether or not there is an address error.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENT NUMBERS 10342096;10671117; 10716375; 10716376;10795407;10795408; AND 10827591 PREVIOUSLY RECORDED AT REEL: 58314 FRAME: 657. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 29, 2024
From: RAKUTEN, INC.
To: RAKUTEN GROUP, INC.
Reel/Frame 068066/0103 →
CHANGE OF NAME Recorded Dec 6, 2021
From: RAKUTEN, INC.
To: RAKUTEN GROUP, INC.
Reel/Frame 058314/0657 →
CHANGE OF ADDRESS Recorded Dec 17, 2015
From: RAKUTEN, INC.
To: RAKUTEN, INC.
Reel/Frame 037751/0006 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2014
From: GLOBAL D, LLC.
To: RAKUTEN, INC.
Reel/Frame 032503/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2014
From: HITACHI, LTD.
To: GLOBAL D, LLC
Reel/Frame 032446/0285 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2006
From: TANAKA, KATSUYA; NAKAMURA, SHUJI
To: HITACHI, LTD.
Reel/Frame 018181/0122 →