Semiconductor integrated circuit including a DRAM and an analog circuit
View Patent ↗A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.
1. A method of fabricating a semiconductor device having a memory cell region and a peripheral region defined on a substrate, said method comprising the steps of:
forming an interlayer insulation film over said substrate so as to cover said memory cell region and said peripheral region;
forming a contact hole in said interlayer insulation film so as to expose a diffusion region in said memory cell region;
forming a mask pattern over said interlayer insulation film so as to cover said peripheral region;
patterning said interlayer insulation film while using said mask pattern as a mask, to reduce a surface level of said interlayer insulation film such that said surface of said interlayer insulation film is lower in said memory cell region than in said peripheral region; and
forming a memory cell capacitor over said interlayer insulation film in a part thereof covering said memory cell region, such that said memory cell capacitor makes a contact with said diffusion region via said contact hole.
2. A method as claimed in claim 1 , wherein said step of forming said memory cell capacitor includes the steps of:
depositing, after said step of patterning said interlayer insulation film, a first conductor film over said interlayer insulation film;
patterning said first conductor film, to form a storage electrode covering said contact hole;
depositing a capacitor dielectric film over said storage electrode;
depositing a second conductor film over said capacitor dielectric film so as to cover a part thereof covering said storage electrode; patterning said second conductor film, to form an opposing electrode;
said step of forming said second conductor film being conducted such that a conductor pattern covering a boundary of said memory cell region and said peripheral region is formed simultaneously with said opposing electrode.