Ultra wide band, differential input/output, high frequency amplifier in an integrated circuit

1. A wide band amplifier comprising:

a core amplifier having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals,

a bandwidth peaking network including (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series, and

the first coil and resistor and the second coil and resistor, respectively, coupled to the core amplifier for receiving the amplified differential output signals,

the bandwidth peaking network includes (a) a first node formed between the first coil and resistor and (b) a second node formed between the second coil and resistor, and

further including a third resistor connected between the first node and the second node.

2. The amplifier of claim 1

wherein the third resistor is free-of current flow at low frequency operation of the amplifier.

3. The amplifier of claim 1 wherein

the first and second resistors have equal resistance values, and

the third resistor has a resistance value substantially similar to the first or second resistor.

4. The amplifier of claim 1 wherein

the bandwidth peaking network is configured to provide a substantially constant gain across the frequency bandwidth of the amplifier.

5. A wideband amplifier comprising:

a core amplifier having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals,

a bandwidth peaking network including (a) a first coil and a first resistor connected in series and (b) a second coil and a second resistor connected in series,

the first coil and resistor and the second coil and resistor, respectively, coupled to the core amplifier for receiving the amplified differential output signals, and

a common mode bias network coupled between the output terminals for providing a voltage bias control feedback signal across the input terminals,

wherein the voltage bias control feedback signal provides a virtual ground common mode potential.

6. The amplifier of claim 5 wherein

the common mode potential across the input terminals is substantially equal to a DC potential across the output terminals.

7. The amplifier of claim 6 wherein

the differential input signals and the amplified differential output signals have substantially the same DC voltage bias.

8. A wide band amplifier comprising

a core amplifier having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals,

the core amplifier including a first amplifier and a second amplifier for receiving the differential input signals,

a bandwidth peaking network including (a) a first coil and a first resistor connected in series, (b) a second coil and a second resistor connected in series, (c) a first node formed between the first coil and first resistor and a second node formed between the second coil and second resistor, and (d) a third resistor connected between the first node and the second node, and

the first amplifier coupled to an end of the first resistor, and the second amplifier coupled to an end of the second resistor,

wherein the bandwidth peaking network is configured to increase the frequency bandwidth of the core amplifier.

9. The amplifier of claim 8 wherein the third resistor is free-of current flow at low frequency operation of the core amplifier.

10. The amplifier of claim 8 wherein the first and second amplifiers each includes:

first and second sub-stages of amplification, and

(a) the first and second sub-stages of amplification of the first amplifier and (b) the first and second sub-stages of amplification of the second amplifier are configured as physically similar to each other on a die.

11. The amplifier of claim 10 wherein

the first sub-stage of amplification of the first amplifier and the first sub-stage of amplification of the second amplifier are formed in a common centroid configuration on the die, and

the second sub-stage of amplification of the first amplifier and the second sub-stage of amplification of the second amplifier are formed in another common centroid configuration on the die.

12. The amplifier of claim 10 wherein

the first sub-stage of amplification of the first amplifier and the first sub-stage of amplification of the second amplifier are biased by a common voltage reference point, and

the second sub-stage of amplification of the first amplifier and the second sub-stage of amplification of the second amplifier are biased by the same common voltage reference point.

13. The amplifier of claim 12 wherein

the common voltage reference point includes a voltage level provided into bases of a plurality of transistors, and

a first collector of the plurality of transistors supplies a first collector current for biasing the first sub-stages of amplification, and

a second collector of the plurality of transistors supplies a second collector current for biasing the second sub-stages of amplification.

14. The amplifier of claim 13 wherein

the first collector current and the second collector current are substantially similar to each other.

15. The amplifier of claim 13 wherein

the first collector current and the second collector current are proportional to each other, based on a ratio of the physical sizes on the die of the respective transistor supplying the first collector current and the respective transistor supplying the second collector current.

16. The amplifier of claim 13 wherein

current levels of the first and second collector currents are adjustable, and

the current levels are adjustable to provide a gain amount of approximately 10 dBv for the core amplifier.

17. A wide band amplifier comprising

a core amplifier having input terminals and output terminals for, respectively, receiving differential input signals and providing amplified differential output signals,

the core amplifier including a first amplifier and a second amplifier for, respectively, receiving the differential input signals,

a bandwidth peaking network including (a) a first coil and a first resistor connected in series, (b) a second coil and a second resistor connected in series, (c) a first node formed between the first coil and first resistor and a second node formed between the second coil and second resistor, and (d) a third resistor connected between the first node and the second node, and

the first amplifier coupled to an end of the first resistor, and the second amplifier coupled to an end of the second resistor,

wherein the bandwidth peaking network is configured to increase the frequency bandwidth of the core amplifier, and

the bandwidth peaking network is configured to provide a substantially constant gain across the frequency bandwidth of the core amplifier.

18. The amplifier of claim 17 further including

a common mode bias network coupled between the output terminals for providing a voltage bias control feedback signal across the input terminals,

wherein the voltage bias control feedback signal provides a virtual ground common mode potential.

19. The amplifier of claim 18 wherein

the common mode potential across the input terminals is substantially equal to a DC potential across the output terminals.

20. The amplifier of claim 19 wherein

the differential input signals and the amplified differential output signals have substantially the same DC voltage bias.