Method for fabricating a semiconductor device

1. A method of fabricating a power semiconductor device, comprising:

covering a surface of a semiconductor body with a mask body;

removing portions of said mask body to define openings extending to said semiconductor body;

removing a portion of said semiconductor body from bottoms of said openings in said mask body to define a plurality of gate trenches and a termination trench disposed around said gate trenches, said trenches being spaced from one another by mesas;

removing said mask body;

oxidizing the sidewalls of said gate trenches;

depositing gate electrode material;

etching back said gate electrode material to leave gate electrodes in said trenches;

implanting channel dopants adjacent said gate trenches after said gate trenches are defined;

forming a source mask;

implanting source dopants through said source mask;

activating said source dopants and said channel dopants to form a base region and source regions;

depositing a low density oxide over said semiconductor body;

depositing a contact mask;

etching said low density oxide through said contact mask;

depositing a metal layer atop said semiconductor body;

forming a front metal mask atop said metal layer; and

etching said metal layer to form at least a source contact, and a gate runner.

2. The method of claim 1 , further comprising,

forming an oxidation retardant body on at least the sidewalls of said gate trenches and at least a sidewall of said termination trench;

growing a thick oxide at the bottom of said gate trenches and said termination trench.

3. The method of claim 2 , further comprising,

removing said oxidation retardant bodies prior to oxidizing said sidewalls of said gate trenches;

oxidizing said mesas;

depositing gate electrode material over said mesas;

etching away gate electrode material from said mesas; and

etching away oxide from said mesas, prior to source implantation.

4. The method of claim 1 , wherein said semiconductor body is epitaxially grown silicon.

5. The method of claim 1 , wherein said mask body is a hard mask comprising of silicon nitride.

6. The method of claim 2 , wherein said oxidation retardant bodies are comprised of silicon nitride.

7. The method of claim 1 , wherein said low density oxide is comprised of TEOS.

8. The method of claim 1 , wherein said gate material is comprised of polysilicon.

9. The method of claim 1 , further comprising defining an EQR opening in said mask body, and removing portions of said semiconductor body to define an EQR around said termination trench.

10. The method of claim 1 , wherein said power semiconductor device is a MOSFET.

11. The method of claim 1 , wherein said semiconductor body is disposed on a semiconductor substrate and further comprising forming a back metal layer over said substrate.