Methods and apparatus for cooling integrated circuits
View Patent ↗A system and method are disclosed which may include measuring a leakage current level of a processor or multiprocessor chip; and storing an indicator value indicative of the leakage current level in a memory associated with the processor or multiprocessor chip.
1. A method, comprising:
measuring respective leakage current levels of a plurality of representative processors;
storing respective indicator values indicative of said leakage current levels in one or more memories associated with said processors; and
establishing a leakage-current measurement range from said respective measured leakage-current levels.
2. The method of claim 1 further comprising adjusting a speed of a fan directing air flow toward at least one of said processors based on said indicator values.
3. The method of claim 1 wherein said storing step comprises storing said respective indicator values in respective memories within said processors.
4. The method of claim 1 wherein said storing step comprises storing said respective indicator values in respective non-volatile memories within said processors.
5. The method of claim 1 further comprising:
associating said leakage current levels with one or more segments of a leakage-current measurement range; and
associating said indicator values with said measurement range segments.
6. The method of claim 1 further comprising:
dividing said leakage-current measurement range into a plurality of measurement range segments; and
associating a separate indicator value with each said measurement range segment.
7. The method of claim 6 wherein said plurality of segments are of equal size.
8. The method of claim 7 wherein said equal-sized segments are quadrants of said measurement range.
9. The method of claim 6 wherein at least two of said segments have different sizes.
10. The method of claim 1 wherein said storing comprises programming one or more of said indicator values into one device selected from the group consisting of: an EPROM (Erasable, Programmable Read-Only Memory), an EEPROM (Electronically, Erasable, Programmable, Read-Only Memory), and a digital fuse.
11. The method of claim 1 , further comprising:
reading one or more of said respective indicator values from said one or more memories; and
establishing a speed of a fan operating to direct air flow toward one or more of said processors, said speed being a function of at least one of said indicator values.
12. The method of claim 11 further comprising storing said respective indicator values in one or more memories within one or more of said processors.
13. The method of claim 11 wherein said reading step comprises reading a digital value indicative of one or more of said leakage currents.
14. The method of claim 13 further comprising storing said respective indicator values in one or more memories in communication with said processors.
15. The method of claim 11 wherein said reading step comprises reading said one or more indicator values from one or more digital fuses within one of said processors.
16. The method of claim 11 wherein said reading step comprises reading said value by a system controller within a multiprocessor system.
17. The method of claim 16 wherein said establishing comprises setting said fan speed by said system controller.
18. The method of claim 11 wherein said establishing comprises setting said fan speed by one or more of said processors.
19. The method of claim 11 wherein said fan is coupled to one or more of said processors.
20. The method of claim 11 wherein said fan speed is also a function of an operational status of at least one of said processors.
21. The method of claim 20 wherein said operational status is one of idle or busy.
22. The method of claim 11 , further comprising reading at least two indicator values for at least two of said processors.
23. An apparatus, comprising:
a plurality of processors;
at least one fan operating to direct air flow toward one or more of said processors;
a memory device in communication with one or more of said processors, said memory device storing respective indicator values indicative of respective leakage current levels of one or more of said processors; and
a controller operating to establish a leakage-current measurement range from said respective measured leakage-current levels, and adjust a speed of the at least one fan directing based on said indicator values.
24. The apparatus of claim 23 wherein said memory device is located within one or more of said processors.
25. The apparatus of claim 23 wherein said memory device is non-volatile.
26. The apparatus of claim 23 wherein said memory device is selected from the group consisting of: an EPROM (Erasable, Programmable Read-Only Memory), and EEPROM (Electronically Erasable, Programmable Read-Only Memory), and a digital fuse.
27. The apparatus of claim 23 wherein said memory device is located on a device other than said processor.
28. The apparatus of claim 23 wherein the controller is a system controller interposed between one or more of said processors and said at least one fan.
29. The apparatus of claim 23 wherein said plurality of processors are incorporated into a multiprocessor system.