Flat panel display including thin film transistor substrate
View Patent ↗A flat panel display includes a plurality of gate lines; a plurality of data lines insulated with the gate lines, the data lines defining a pixel by intersecting the gate line; and a thin film transistor (TFT) being provided in each of the pixels and containing an organic semiconductor layer, wherein a distance between the adjacent TFTs in a direction extended to the gate line is longer than a width of the pixel in a direction extended to the gate line.
1. A flat panel display, comprising:
a plurality of gate lines for providing a gate signal to a gate electrode;
a plurality of data lines insulated from the gate lines;
a plurality of pixels disposed in an intersection of data lines and gate lines, each pixel divided into a upper region, a middle region, and a lower region; and
a plurality of thin film transistors (TFT), each of the TFTs are disposed in the one of pixels and includes the gate electrode,
wherein a first pixel and a second pixel of the pixels are adjacent to each other along one of the respective gate lines,
wherein a first TFT of the plurality of TFTs is provided in the middle region of the first pixel, and a second TFT of the plurality of TFTs is provided in the lower region of the second pixel.
2. The flat panel display according to claim 1 , further comprising a branch gate line branched from the gate line and extended along the data line while being adjacent to the data line, wherein the first TFT is connected to the branch gate line.
3. The flat panel display according to claim 2 , wherein the branch gate line is extended to the middle region of the first pixel.
4. The flat panel display according to claim 1 , wherein the first and the second pixels are alternatingly arranged relative to each other.
5. The flat panel display according to claim 1 , wherein the distance between the adjacent TFTs is between about 1.2 to about 3.16 times larger than a width of the pixel.
6. The flat panel display according claim 1 , wherein each of the TFTs contain an organic semiconductor layer formed by an inkjet method.
7. The flat panel display according to claim 1 , wherein each of the TFTs further includes a source electrode and a drain electrode spaced apart to define a channel region, with the gate electrode interposed therebetween, and an organic semiconductor layer formed in the channel region.
8. The flat panel display according to claim 7 , further comprising a bank for surrounding the channel region and for exposing at least a portion of each of the source electrode and the drain electrode, wherein the organic semiconductor layer is formed inside the bank.
9. The flat panel display according to claim 8 , wherein a surface of the bank has water repellency and oil repellency.
10. The flat panel display according to claim 7 , wherein each the source and the drain electrodes is made of one of ITO and IZO.
11. The flat panel display according to claim 7 , wherein the organic semiconductor layer comprises one of a derivative containing tetracene or pentacene substituents; oligothiophene having 4 to 8 thiophene rings coupled to each other through 2 and 5 positions of thiophene rings; perylenetetracarboxylic dianhydride (PTCDA) or an imide derivative thereof; naphthalenetetracarboxylic dianhydride (NTCDA) or an imide derivative thereof; metallized pthalocyanine or a halogenated derivative thereof; perylene or coronene and a derivative containing substituents thereof; co-oligomer or co-polymer of thienylene and vinylene; thiophene thienylene or coronene, and a derivative containing substituents thereof; and a derivative containing one or more hydrocarbon chains of 1 to 30 carbons in an aromatic or heteroaromatic ring of said materials.
12. The flat panel display according to claim 7 , wherein the organic semiconductor layer is soluble in an aqueous solution or organic solvent.
13. The flat panel display according to claim 1 , wherein the TFT further comprises a light shielding film; wherein an insulation film covers the light shielding film; a source electrode and a drain electrode spaced apart defining a channel region, with the light shielding film interposed therebetween; and an organic semiconductor layer formed on the channel region.
14. The flat panel display according to claim 13 , further comprising a gate electrode formed at a location corresponding to the light shielding film on the organic semiconductor layer, and a first protection film interposed between the organic semiconductor layer and the gate electrode.
15. The flat panel display according to claim 1 , wherein each TFT has four nearest neighbors of the TFTs spaced apart by the same distance.
16. The flat panel display according to claim 15 , wherein each TFT has four next nearest neighbors of the TFTs spaced apart by the same distance.