Scan path circuit and semiconductor integrated circuit comprising the scan path circuit
View Patent ↗Each of D flip-flops (FFs) 13 a to 13 f constituting a scan path circuit has a normal operation input circuit to be selected in a normal operation and a test operation input circuit to be selected in a test operation, and a control signal having an intermediate voltage between a supply voltage and a ground voltage is sent from a voltage generating circuit 17 to the test operation input circuit of each FF in the test operation. In this case, the amount of an output change in data in each FF is smoother than that in the case in which the supply voltage is applied. Consequently, the delay time of the data is increased. The intermediate voltage to be applied to each FF in the test operation is determined based on a feedback signal sent from a test circuit 15 for checking whether scanned-out data have an error or not.
1. A scan path circuit constituted by a plurality of flip-flops which is operated as a shift register in a separate mode in which a number of logical steps from an input terminal to an output terminal is different from a normal mode, each of the flip-flops comprising:
an input circuit for inputting data in a predetermined timing;
an output circuit for outputting predetermined data corresponding to the data input to the input circuit; and
a terminal to which a control signal is applied,
wherein each of said plurality of flip-flops controls the delay time for outputting data from a time in which the data is input to the respective flop-flop,
and wherein the delay time is controlled based on the control signal.
2. The scan path circuit according to claim 1 , wherein the control signal is a power supply voltage applied to a source of a MOS transistor included in the flip-flop.
3. The scan path circuit according to claim 1 , wherein the control signal is a substrate bias voltage applied to a substrate of a MOS transistor included in the flip-flop.
4. The scan path circuit according to claim 1 , wherein the control signal is a power supply voltage applied to a source of a MOS transistor included in the input circuit of the flip-flop.
5. The scan path circuit according to claim 1 , wherein the control signal is a substrate bias voltage applied to a substrate of a MOS transistor included in the input circuit of the flip-flop.
6. The scan path circuit according to claim 1 , wherein the delay time is varied in the normal mode and the separate mode from the normal mode.
7. The scan path circuit according to claim 6 , wherein the input circuit includes a first input circuit which is selected in the normal mode and data is input in a predetermined timing in the normal mode and a second input circuit which is selected in the separate mode which is different from the normal mode and data is input in a predetermined timing in the separate mode.
8. The scan path circuit according to claim 7 , wherein the first input circuit and/or the second input circuit is constituted by a tri-state inverter circuit to be controlled by the control signal and the input data,
and an output of the tn-state inverter circuit is connected in common.
9. The scan path circuit according to claim 8 , wherein the tri-state inverter circuit applies a voltage having the same level as that of the control signal in place of a supply voltage and applies a voltage having a value obtained by subtracting the voltage having the same level as that of the control signal from the supply voltage in place of a ground voltage in the normal mode.
10. The scan path circuit according to claim 8 , wherein a substrate bias voltage of the tn-state inverter circuit is the voltage having the same level as that of the control signal or a voltage having a value obtained by subtracting the voltage having the same level as that of the control signal from a supply voltage in the normal mode.
11. The scan path circuit according to claim 7 , wherein the first input circuit and/or the second input circuit is constituted by a transfer gate circuit to be controlled by the control signal and the input data, and
an output of the transfer gate circuit is connected in common.
12. The semiconductor circuit according to claim 6 , wherein the voltage having the same level as that of the control signal is applied in place of a supply voltage of the flip-flop and a voltage having a value obtained by subtracting the voltage having the same level as that of the control signal from the supply voltage is applied in place of a ground voltage of the flip-flop in the separate mode from the normal mode.
13. A data holding circuit comprising:
an input circuit for inputting data in a predetermined timing; and
an output circuit for outputting predetermined data corresponding to the data input to the input circuit,
wherein the data holding circuit controls the delay time for outputting data from a time in which the data is input to the respective flop-flop,
wherein the delay time is varied in a normal mode and a separate mode in which the number of logical steps from an input terminal to an output terminal are different from the normal mode.
14. The data holding circuit according to claim 13 , wherein said data holding circuit is a flip-flop which is used for one of the flip-flops in a scan path circuit.