IP Library Granted Patent US 7,953,991
Granted Patent B2
US 7,953,991 · App. 11/507,378 · Granted May 31, 2011

Processing system and methods for use therewith

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Quick Facts
Patent No.
US 7,953,991
App. No.
11/507,378
Granted
May 31, 2011
Kind
B2
Abstract

A processing system includes a processing module and a memory module for storing plurality of data. A controllable power source supplies a source voltage to the memory module in response to a target voltage. A controller module receives a temperature signal and adjusts the target voltage in response to the temperature signal.

Claims (50)

1. A system on a chip integrated circuit comprising:

a processing module;

a memory module, operably coupled to the processing module, for storing a plurality of data;

a controllable power source, operably coupled to the memory module, for supplying a source voltage to the memory module in response to a target voltage; and

a controller module, operably coupled to the memory module and the controllable power source, for receiving a temperature signal and further operable to:

compare the temperature signal to a first temperature threshold;

increase the target voltage as a first function of the difference between the temperature signal and the first temperature threshold, when the temperature signal indicates that a temperature of the memory module is below the first temperature threshold;

compare the temperature signal to a second temperature threshold;

increase the target voltage as a second function of the difference between the temperature signal and the second temperature threshold, when the temperature signal indicates that the temperature of the memory module is above the second temperature threshold, wherein the second temperature threshold is greater than the first temperature threshold; and

when the temperature signal indicates that the temperature of the memory module is between the first and second temperature thresholds, maintain the target voltage at a current level.

2. The system on a chip integrated circuit of claim 1 further comprising: a controllable refresh clock generator for supplying a refresh clock signal to the memory module, the refresh clock signal having a refresh clock frequency that is based on a target refresh clock frequency; wherein the controller module increases the target refresh clock frequency when the temperature signal compares unfavorably to the second temperature threshold.

3. The system on a chip integrated circuit of claim 1 further comprising:

a controllable system clock generator for supplying a system clock signal to the memory module, the system clock signal having a system clock frequency that is based on a target system clock frequency;

wherein the controller module increases the target system clock frequency when the temperature signal compares unfavorably to the second temperature threshold.

4. The system on a chip integrated circuit of claim 3 wherein the controller module decreases the system clock frequency when the temperature signal compares unfavorably to the second temperature threshold.

5. The system on a chip integrated circuit of claim 1 wherein at the first function is a monotonically decreasing function, and the second function is a monotonically increasing function.

6. A processing system comprising:

a processing module;

a memory module, operably coupled to the processor, for storing plurality of data;

a controllable power source, operably coupled to the memory module, for supplying a source voltage to the memory module in response to a target voltage; and

a controller module, operably coupled to the memory module and the controllable power source, for receiving a temperature signal, comparing the temperature signal to a first temperature threshold and to a second temperature threshold that is greater than the first temperature threshold, for increasing the target voltage when the temperature signal indicates that a temperature of the memory module is below the first temperature threshold or is above the second temperature threshold, and for maintaining the target voltage at a current level when the temperature signal indicates that the temperature of the memory module is between the first and second temperature thresholds.

7. The processing system of claim 6 , wherein the controller module increases the target voltage as a first function of the difference between the temperature signal and the first temperature threshold.

8. The processing system of claim 6 , wherein the controller module increases the target voltage as a second function of the difference between the temperature signal and the second temperature threshold.

9. The processing system of claim 6 , further comprising:

a controllable refresh clock generator for supplying a refresh clock signal to the memory module, the refresh clock signal having a refresh clock frequency that is based on a target refresh clock frequency;

wherein the controller module increases the target refresh clock frequency when the temperature signal compares unfavorably to a third temperature threshold.

10. The processing system of claim 9 further comprising:

a controllable system clock generator for supplying a system clock signal to the memory module, the system clock signal having a system clock frequency that is based on a target system clock frequency;

wherein the controller module decreases the target system clock frequency when the temperature signal compares unfavorably to the third temperature threshold.

11. The processing system of claim 9 wherein the third temperature threshold is equal to the second temperature threshold.

12. The processing system of claim 6 wherein at least one of: the processing module, the memory module, the controllable power source and the controller module, are implemented on a system on a chip integrated circuit.

13. A method comprising:

receiving a temperature signal;

making a first comparison between the temperature signal and a first temperature threshold;

making a second comparison between the temperature signal and a second temperature threshold that is greater than the first temperature threshold;

adjusting a source voltage to a memory module in response to the first comparison and the second comparison, by increasing the source voltage when the temperature signal indicates that a temperature is either below the first temperature threshold or above the second temperature threshold; and

maintaining the source voltage at a current level when the temperature signal indicates that the temperature of the memory module is between the first and second temperature thresholds.

14. The method of claim 13 , wherein the step of increasing the source voltage includes increasing the source voltage as a first function of a difference between the temperature signal and the first temperature threshold.

15. The method of claim 14 wherein the first function is a monotonic function.

16. The method of claim 13 , wherein the step of increasing the source voltage includes increasing the source voltage as a second function of a difference between the temperature signal and the second temperature threshold.

17. The method of claim 16 wherein the second function is a monotonic function.

18. The method of claim 13 , further comprising the step of:

increasing a refresh clock frequency when the temperature signal compares unfavorably to a third temperature threshold.

19. The method of claim 18 further comprising the step of:

controlling a system clock frequency based on the refresh clock frequency when the temperature signal compares unfavorably to the third temperature threshold.

20. The method of claim 19 wherein the step of controlling a system clock frequency includes decreasing the system clock frequency when the temperature signal compares unfavorably to the third temperature threshold.

21. The method of claim 18 wherein the third temperature threshold is equal to the second temperature threshold.

22. The system on a chip integrated circuit of claim 1 , wherein the first function and the second function are linear functions.

23. The system on a chip integrated circuit of claim 1 , wherein the first function and the second function are non-linear functions.

24. The system on a chip integrated circuit of claim 1 , wherein the first function and the second function are symmetrical functions.

Assignments (17)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2025
From: NXP USA, INC.
To: ASCALE TECHNOLOGIES LLC
Reel/Frame 070026/0838 →
CHANGE OF NAME Recorded Aug 31, 2017
From: SIGMATEL, INC.
To: SIGMATEL, LLC
Reel/Frame 043735/0306 →
MERGER Recorded Jul 26, 2017
From: SIGMATEL, LLC
To: NXP USA, INC.
Reel/Frame 043328/0351 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
SECURITY AGREEMENT Recorded Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →
SECURITY AGREEMENT Recorded Jun 17, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030628/0636 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded May 10, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024358/0439 →
SECURITY AGREEMENT Recorded Mar 16, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A.
Reel/Frame 024079/0406 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Jul 9, 2008
From: SIGMATEL, INC.
To: CITIBANK, N.A.
Reel/Frame 021212/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2006
From: HENSON, MATTHEW BRADY; MULLIGAN, DANIEL
To: SIGMATEL, INC.
Reel/Frame 018371/0372 →