CMOS pixel with dual gate PMOS
View Patent ↗A pixel circuit with a dual gate PMOS is formed by forming two P + regions in an N − well. The N − well is in a P − type substrate. The two P + regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N − well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N − well potential so that they remain reverse biased with respect to the N − well. One of the P + regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N − well forms a second gate for the dual gate PMOS transistor since the potential of the N − well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N − well.
1. A method of operating a pixel circuit, comprising:
providing a P − silicon substrate;
providing an N − well formed in said P − silicon substrate, wherein said N − well and said P − silicon substrate form a PN junction which can accumulate signal-generated charge;
providing a first P + region, a second P + region, and a third P + region formed in said N − well;
providing a first PMOS transistor having a source, a drain, and a channel formed in said N − well, wherein said first P + region forms said source of said first PMOS transistor, said second P + region forms said drain of said first PMOS transistor, and that part of said N − well between said first P + region and said second P + region forms said channel of said first PMOS transistor;
providing a second PMOS transistor having a source, a drain, and a channel formed in said N − well, wherein said third P + region forms said source of said second PMOS transistor, said second P + region forms said drain of said second PMOS transistor, and that part of said N − well between said second P + region and said third P + region forms said channel of said second PMOS transistor;
providing a first gate electrode formed over a gate oxide over said channel of said first PMOS transistor, thereby forming the gate of said first PMOS transistor;
providing a second gate electrode formed over a gate oxide over said channel of said second PMOS transistor, thereby forming the gate of said second PMOS transistor;
providing a first NMOS transistor having a drain connected to a first output node, a gate, and a source connected to said source of said first PMOS transistor;
providing a first N + region formed in said N − well;
providing a second NMOS transistor having a source connected to said first N + region formed in said N − well, a drain connected to said gate of said first NMOS transistor, and a gate connected to said source of said first NMOS transistor;
providing a third NMOS transistor having a drain connected to a second output node, a gate, and a source connected to said source of said second PMOS transistor;
providing a second N + region formed in said N − well;
providing a fourth NMOS transistor having a source connected to said second N + region formed in said N − well, a drain connected to said gate of said third NMOS transistor, and a gate connected to said source of said third NMOS transistor;
resetting the potential of said junction between said N − well and said P − silicon substrate by raising the potential of said second P + region from ground potential to the highest potential in the pixel circuit while holding said gates of said first PMOS transistor and said second PMOS transistor at ground potential during a reset period;
raising the potential of said gate of said second PMOS transistor to the highest potential in the circuit while holding the potential of said second P + region at the highest potential in the circuit and said gate of said first PMOS transistor at ground potential during a transition period wherein said transition period immediately follows said reset period; and
holding the potential of said gate of said second PMOS transistor at the highest potential in the circuit and setting the potential of said second P + region at ground potential during a charge integration period wherein said charge integration period immediately follows said transition period.
2. The method of claim 1 further comprising holding the potential of said second P + region at ground potential and setting the potential of said gate of said second PMOS transistor at ground potential after said charge integration period has been completed thereby storing a signal related to the charge accumulated by said PN junction between said N − well and said P − silicon substrate during said charge integration period at said gate of said first NMOS transistor.
3. The method of claim 1 further comprising:
holding the potential of said second P + region at ground potential and setting the potential of said gate of said second PMOS transistor at ground potential after said charge integration period has been completed;
determining the potential difference between said second output node and said first output node after said charge integration period has been completed, the potential of said gate of said second PMOS transistor has been set to ground potential, and the potential of said second P+ region is held at ground potential, wherein said potential between said first output node and said second output node is related to the charge accumulated by said PN junction between said N − well and said P − silicon substrate during said charge integration period.
4. A method of operating a pixel circuit, comprising:
providing an N − silicon substrate;
providing a P − well formed in said N − silicon substrate, wherein said P − well and said N − silicon substrate form a PN junction which can accumulate signal-generated charge;
providing a first N + region, a second N + region, and a third N + region formed in said P − well;
providing a first NMOS transistor having a source, a drain, and a channel formed in said P − well, wherein said first N + region forms said source of said first NMOS transistor, said second N + region forms said drain of said first NMOS transistor, and that part of said P − well between said first N + region and said second N + region forms said channel of said first NMOS transistor;
providing a second NMOS transistor having a source, a drain, and a channel formed in said P − well, wherein said third N + region forms said source of said second NMOS transistor, said second N + region forms said drain of said second NMOS transistor, and that part of said P − well between said second N + region and said third N + region forms said channel of said second NMOS transistor;
providing a first gate electrode formed over a gate oxide over said channel of said first NMOS transistor, thereby forming the gate of said first NMOS transistor;
providing a second gate electrode formed over a gate oxide over said channel of said second NMOS transistor, thereby forming the gate of said second NMOS transistor;
providing a first PMOS transistor having a drain connected to a first output node, a gate, and a source connected to said source of said first NMOS transistor;
providing a first P + region formed in said P − well;
providing a second PMOS transistor having a source connected to said first P + region formed in said P − well, a drain connected to said gate of said first PMOS transistor, and a gate connected to said source of said first PMOS transistor;
providing a third PMOS transistor having a drain connected to a second output node, a gate, and a source connected to said source of said second NMOS transistor;
providing a second P + region formed in said P − well;
providing a fourth PMOS transistor having a source connected to said second P + region formed in said P − well, a drain connected to said gate of said third PMOS transistor, and a gate connected to said source of said third PMOS transistor;
resetting the potential of said junction between said P − well and said N − silicon substrate by changing the potential of said second N + region from ground potential to the lowest potential in the pixel circuit while holding said gates of said first NMOS transistor and said second NMOS transistor at ground potential during a reset period;
changing the potential of said gate of said second NMOS transistor to the lowest potential in the circuit while holding the potential of said second N + region at the lowest potential in the circuit and said gate of said first NMOS transistor at ground potential during a transition period wherein said transition period immediately follows said reset period; and
holding the potential of said gate of said second NMOS transistor at the lowest potential in the circuit and setting the potential of said second N + region at ground potential during a charge integration period wherein said charge integration period immediately follows said transition period.
5. The method of claim 4 further comprising holding the potential of said second N + region at ground potential and setting the potential of said gate of said second NMOS transistor at ground potential after said charge integration period has been completed thereby storing a signal related to the charge accumulated by said PN junction between said P − well and said N − silicon substrate during said charge integration period at said gate of said first PMOS transistor.
6. The method of claim 4 further comprising:
holding the potential of said second N + region at ground potential and setting the potential of said gate of said second NMOS transistor at ground potential after said charge integration period has been completed;
determining the potential difference between said second output node and said first output node after said charge integration period has been completed, the potential of said gate of said second NMOS transistor has been set to ground potential, and the potential of said second N+ region is held at ground potential, wherein said potential between said first output node and said second output node is related to the charge accumulated by said PN junction between said P − well and said N − silicon substrate during said charge integration period.