Memory device configured to refresh memory cells in a power-down state

1. A memory, comprising:

a memory cell array including a plurality of memory cell blocks, wherein each memory cell block has a plurality of non-volatile memory cells;

an access operation detecting portion configured to detect an access operation for a prescribed number of the memory cells; and

a refresh portion configured to rewrite data in the memory cells, to read data from and rewrite data to the memory cells in a power-down state, and to read data from and rewrite data to the memory cells included in at least one of the memory cell blocks of the prescribed number of memory cells based on at least the detected access operation.

2. The memory of claim 1 , further comprising a power-down detecting portion configured to detect the power-down state, wherein in response to the power-down detecting portion detecting the power-down state, the refresh portion is further configured to read data from and rewrite data to the memory.

3. The memory of claim 2 , wherein the power-down detecting portion is further configured to output an activation signal to drive the refresh portion in response to detection of the power-down state.

4. The memory of claim 1 , further comprising a row decoder configured to drive a word line, wherein the refresh portion is further configured to output a control signal to the row decoder in the power-down state and wherein the control signal is configured to start a refresh operation including a read operation and a rewrite operation.

5. The memory of claim 1 , wherein:

the memory is configured to generate a power-down signal to be inputted to the refresh portion in response to the power-down state; and

the refresh portion is further configured to read data from and rewrite data to the memory based on the power-down signal.

6. The memory of claim 1 , further comprising:

a first access frequency-detecting portion configured to detect an access frequency of a particular memory cell, wherein the refresh portion is further configured to read data from and rewrite data to the particular memory cell if at least the first access frequency-detecting portion detects that a total access frequency of the particular memory cell reaches a prescribed threshold.

7. The memory of claim 1 , wherein:

the access operation detecting portion comprises a first holding portion configured to hold a presence/absence of the access operation for each of the memory cell blocks; and

the refresh portion is further configured to read data from and rewrite data to the memory cells included in the at least one memory cell block if at least the first holding portion holds the presence of the access operation of the corresponding at least one memory cell block.

8. The memory of claim 7 , wherein the first holding portion is provided to each of the memory cell blocks.

9. The memory of claim 1 , wherein:

the access operation detecting portion comprises a second access frequency-detecting portion configured to detect an access frequency for each of the memory cell blocks; and

the refresh portion is further configured to read data from and rewrite data to the memory cells included in the at least one memory cell block if at least the second access frequency-detecting portion detects that the access frequency of the corresponding memory cell block has reached a prescribed threshold.

10. The memory of claim 1 , further comprising a plurality of word lines connected to the prescribed number of memory cells respectively, wherein:

the access operation detecting portion includes a second holding portion configured to hold a presence/absence of an access operation for each of the word lines; and

the refresh portion is further configured to read data from and rewrite data to the memory cells included in the at least one memory cell block corresponding to at least one of the word lines if at least the second holding portion holds the presence of the access operation of the corresponding at least one word line.

11. The memory of claim 10 , wherein the second holding portion is provided to each of the word lines.

12. The memory of claim 10 , further comprising a second access frequency-detecting portion configured to detect an access frequency for each of the memory cell blocks and to change the second holding portions corresponding to the at least one memory cell block into states that hold an absence of access operations if all the second holding portions corresponding to the at least one memory cell block hold a presence of access operations if the second access frequency-detecting portion detects that the access frequency of the at least one memory cell block has reached a prescribed threshold, wherein the refresh portion is configured to neither read data from nor rewrite data to the memory cells included in the at least one memory cell block if all the second holding portions corresponding to the at least one memory cell block hold an absence of access operations.

13. The memory of claim 12 , wherein the refresh portion is configured to read data from and rewrite data to the memory cells included in the at least one memory cell block if the second holding portions corresponding to the at least one memory cell block include both the second holding portion that holds the presence of an access operation and the second holding portion that holds the absence of an access operation if the second access frequency-detecting portion detects that an access frequency of the at least one memory cell block has reached the prescribed threshold.

14. The memory of claim 12 , wherein the second access frequency-detecting portion is provided to each of the memory cell blocks.

15. The memory according to claim 1 , wherein the memory cell comprises a ferroelectric capacitor having a ferroelectric film.

16. A memory apparatus, comprising:

a memory cell array including a plurality of memory cell blocks, wherein each memory cell block has a plurality of non-volatile memory cells;

an access operation detecting portion including a first holding portion configured to hold a presence/absence of an access operation for each of the memory cell blocks; and

refresh portion means for rewriting data in a memory cell of the plurality of non-volatile memory cells, wherein the refresh portion means reads data from and rewrites data to the memory cell of the plurality of non-volatile memory cells in a power-down state.

17. The memory apparatus of claim 16 , further comprising power-down detecting means for detecting the power-down state, wherein the refresh portion means reads data from and rewrites data to the memory cell of the plurality of non-volatile memory cells if the power-down detecting means detects the power-down state.

18. The memory apparatus of claim 16 wherein the access operation detecting portion is configured to detect the access operation for a prescribed number of the memory cells, and wherein the refresh portion means reads data from and rewrites data to the memory cells included in at least one of the memory cell blocks possessing the prescribed number of memory cells based on at least a detection of the access operation.

19. The memory apparatus of claim 16 , wherein the non-volatile memory cells comprise ferroelectric memory cells.

20. An apparatus, comprising:

a non-volatile memory configured to enter a power-down state and including a plurality of memory cell blocks

an access operation detection portion including a first holding portion means for holding a presence/absence of an access operation for each of the memory cell blocks; and

a refresh control circuit coupled to the non-volatile memory and configured to read data from and rewrite data to a memory cell of the non-volatile memory in the power-down state.

21. The apparatus of claim 20 , wherein:

the non-volatile memory is further configured to generate a power-down signal; and

the non-volatile memory is further configured to input the generated power-down signal to the refresh control circuit to initiate a refresh operation in response to entry into the power-down state, wherein the refresh control circuit is further configured to initiate the refresh operation to read data from and rewrite data to the memory cell based on the power-down signal.

22. The apparatus of claim 20 , further comprising:

an access detection portion configured to detect an access frequency of the memory cell, wherein the refresh control circuit is further configured to read data from and rewrite data to the memory cell if the access detection portion detects that a total access frequency of the memory cell has reached a prescribed threshold.

23. The apparatus of claim 20 , wherein the non-volatile memory comprises a ferroelectric memory.