Method of manufacturing a thin film transistor array panel

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line on a substrate;

depositing a gate insulating layer and a semiconductor layer in sequence on the gate line;

depositing a lower conductive film and an upper conductive film on the semiconductor layer;

photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer;

depositing a passivation layer;

photo-etching the passivation layer to expose first and second portions of the upper conductive film;

removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film;

forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film;

removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and

forming a columnar spacer on the exposed portion of the semiconductor layer.

2. The method of claim 1 , wherein the photo-etching of the passivation layer comprises:

exposing the first portion of the upper conductive film and a portion of the gate insulating layer adjacent to the first portion.

3. The method of claim 2 , wherein the exposed portion of the gate insulating layer is covered with the pixel electrode along with the first portion of the lower conductive film.

4. The method of claim 3 , wherein the photo-etching of the passivation layer further comprises:

exposing a third portion of the upper conductive film.

5. The method of claim 4 , wherein the removal of the first and the second portions of the upper conductive film comprises:

removing the third portion of the upper conductive film to expose a third portion of the lower conductive film.

6. The method of claim 5 , wherein the gate line comprises a lower film and an upper film.

7. The method of claim 6 , wherein the photo-etching of the passivation layer further comprises:

etching the gate insulating layer to expose a portion of the upper film of the gate line.

8. The method of claim 7 , wherein the removal of the first and the second portions of the upper conductive film comprises:

removing the exposed portion of the upper film of the gate line to expose a portion of the lower film of the gate line.

9. The method of claim 7 , further comprising:

forming a contact assistant on the third portion of the lower conductive film and the exposed portion of the lower film of the gate line.

10. The method of claim 9 , wherein the upper film of the gate line comprises the same material as the upper conductive film.

11. The method of claim 10 , wherein the upper film of the gate line and the upper conductive film comprises Cr and the lower film of the gate line and the lower conductive film comprises Al or Al-Nd alloy.

12. The method of claim 11 , wherein the pixel electrode and the redundant electrodes comprise IZO.

13. The method of claim 12 , wherein the formation of a pixel electrode and a pair of redundant electrodes and the removal of the exposed part of the second portion of the lower conductive film are simultaneously performed.

14. The method of claim 12 , wherein the formation of a pixel electrode and a pair of redundant electrodes and the removal of the exposed part of the second portion of the lower conductive film are performed under the same etch condition.

15. The method of claim 1 , wherein the semiconductor layer comprises an intrinsic film and an extrinsic film, and

the method further comprises:

removing the exposed portion of the extrinsic film after removing the second portion of the lower conductive film.