Systems and methods for resolving signal-to-noise ratio margin difference in dual latency discrete multi-tone-based xDSL systems under colored noise conditions
View Patent ↗Systems and methods for resolving signal-to-noise ratio margin difference n dual latency discrete multi-tone (DMT)-based xDSL systems under colored noise conditions. Rather than assuming a constant power spectral density (PSD) for noise over fast and interleaved data paths of a dual latency system, band edges vulnerable to colored noise are determined and data on the fast data path is allocated away from these band edges. Also, receive windowing may be used to further enhance performance.
1. A method of resolving a signal-to-noise (SNR) margin difference between fast and interleaved channels in a dual latency discrete multi-tone (DMT)-based digital subscriber line (DSL) communication system comprising:
dividing a communication channel into a plurality of equal bandwidth sub-channels;
determining the transmission characteristics of each sub-channel;
establishing two data paths from the sub-channels, wherein the data paths have different target SNR margins;
allocating data having a relatively higher SNR margin near band edges between upstream and downstream data bands on the communication channel and allocating data having a relatively lower SNR margin away from these band edges, wherein establishing two data paths from the sub-channels comprises establishing at least a relatively fast data path and a relatively slower data path, wherein establishing a relatively fast data path comprises establishing a data path having a relatively higher bit error rate than the relatively slower data path, wherein data to be transferred over the relatively slower data path is allocated to tones near the band edge; and
backing off a pre-determined number of tones at the band edges in the data path having the relatively higher bit error rate.
2. The method according to claim 1 , further comprising simultaneously transferring bits of data over the two data paths.
3. The method according to claim 1 , wherein establishing a relatively slower data path comprises establishing a data path comprising at least one forward error correction (FEC) technique selected from the group consisting of Reed-Solomon coding, interleaving, and Trellis coding.
4. The method according to claim 3 , wherein establishing a relatively fast data path and a relatively slower data path comprises establishing data paths having different coding gains, wherein the sub-channels on the relatively slower data path have a higher coding gain than sub-channels on the relatively fast data path.
5. The method according to claim 3 , wherein the establishing a relatively fast data path and a relatively slower data path comprises applying different target noise margins to sub-channels carrying different latency paths.
6. The method according to claim 3 , wherein data corresponding to error sensitive applications is transferred over the relatively slower data path.
7. The method according to claim 6 , wherein data corresponding to latency sensitive application is transferred over the relatively faster data path.
8. The method according to claim 1 , further comprising performing receive windowing on data received over the received data from both paths.
9. The method according to claim 8 , wherein performing receive windowing comprises performing windowing with a window half beta=512.
10. The method according to claim 8 , wherein performing receive windowing comprises performing windowing with a window half beta=256.
11. The method according to claim 8 , wherein performing receive windowing comprises performing windowing with a window half beta=128.
12. The method according to claim 8 , wherein performing receive windowing comprises performing windowing with a window half beta=64.
13. A method of reducing performance variation between fast and interleaved data paths in a dual latency discrete multi-tone (DMT)-based digital subscriber line (DSL) system comprising:
dividing a communication channel into a plurality of equal bandwidth tones;
allocating the plurality of tones into fast and interleaved data paths;
determining band edges between upstream and downstream data bands on the communication channel that are vulnerable to colored, non-constant noise; and
allocating tones in the fast data path away from the band edges, wherein allocating the plurality of tones into fast and interleaved data paths comprises establishing a data path having a relatively higher bit error rate than a relatively slower data path, wherein data to be transferred over the relatively slower data path is allocated to tones near the band edge; and
backing off a pre-determined number of tones at the band edges in the data path having the relatively higher bit error rate.
14. The method according to claim 13 , further comprising performing a receive windowing function on data transmitted on the fast and interleaved data paths.
15. A chipset for a digital subscriber line (DSL) transceiver comprising:
circuitry adapted to determined conditions of a communication line between a customers premises and a central office;
circuitry adapted to divide the communication line into a plurality of equal bandwidth sub-channels;
circuitry adapted to allocate the plurality of equal bandwidth sub-channels into first and second parallel data paths, wherein the first data path is characterized as a being a relatively faster data path and the second data paths is characterize as being an interleaved data path such that the relatively fast data path has a relatively higher bit error rate than the second data path, wherein data to be transferred over the second data path is allocated to tones near the band edge;
circuitry adapted to determine band edges between upstream and downstream data bands on the communication channel that are vulnerable to colored noise; and
circuitry adapted to allocate data onto sub-carriers in the relatively faster data path away from the band edges; and
circuitry adapted to back off a pre-determined number of tones at the band edges in the data path having the relatively higher bit error rate.
16. The chipset according to claim 15 , further comprising circuitry adapted to perform a windowing function on data received over the two parallel data paths.