Semiconductor memory
View Patent ↗A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
1. A semiconductor memory comprising:
a first memory cell and a plurality of second memory cells;
complementary bit lines connected to said first and second memory cells;
a sense amplifier connected to said complementary bit lines;
a refresh control circuit for cyclically outputting a refresh control signal for refreshing said first and second memory cells; and
an operation control circuit for performing a read operation, a write operation, and a refresh operation on said first and second memory cells, wherein
said operation control circuit
operates any of said first and second memory cells selected in accordance with an address signal during normal operation mode in which said read operation and said write operation are performed, and
performs, at the start of low power consumption mode, a refresh operation in which data retained in said first memory cell is amplified by said sense amplifier and written to said first and second memory cells, and subsequently refreshes said first and second memory cells simultaneously in response to said refresh control signal.
2. The semiconductor memory according to claim 1 , wherein:
at least one of said second memory cells is connected to a first bit line which is one of said complementary bit lines, said first bit line being connected to said first memory cell; and
at least two of the rest of said second memory cells are connected to a second bit line which is another of said complementary bit lines.
3. The semiconductor memory according to claim 1 , comprising
a first word line connected to said first memory cell and second word lines connected to said second memory cells, respectively, wherein
said operation control circuit starts selection of said first word line earlier than selection of said second word lines during a first refresh operation in said low power consumption mode.
4. The semiconductor memory according to claim 3 , wherein
said operation control circuit selects said second word lines in succession after the selection of said first word line.
5. The semiconductor memory according to claim 1 , comprising
a first word line connected to said first memory cell and second word lines connected to said second memory cells, respectively, wherein
said word line control circuit selects said first and second word lines simultaneously during second and subsequent refresh operations in said low power consumption mode.
6. The semiconductor memory according to claim 1 , wherein
said operation control circuit refreshes, in response to said refresh control signal, either of said first and second memory cells selected in accordance with said address signal during said normal operation mode, and refreshes both of said first and second memory cells in response to a single operation of said sense amplifier during said low power consumption mode.
7. The semiconductor memory according to claim 1 , wherein
said refresh control circuit outputs said refresh control signal at first intervals during said normal operation mode, and outputs said refresh control signal at second intervals longer than said first intervals during second and subsequent refresh operations in said low power consumption mode.
8. The semiconductor memory according to claim 7 , wherein
in shifting from said low power consumption mode to said normal operation mode, said refresh control circuit outputs said refresh control signal at third intervals shorter than said first intervals.
9. The semiconductor memory according to claim 1 , comprising
a command terminal for receiving a first command and a second command, wherein
the semiconductor memory enters said low power consumption mode when said first command is received at said command terminal in said normal operation mode, and enters said normal operation mode when said second command is received at said command terminal in said low power consumption mode.