Thin film transistor array panel and manufacturing method thereof
View Patent ↗A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a pair of first and second gate members on a substrate;
forming a gate insulating layer on the first and the second gate members;
forming a pair of first and second semiconductor members on the gate insulating layer;
forming a pair of first and second source members and a pair of first and second drain members over the pair of first and second semiconductor members;
forming a passivation layer on the substrate including the gate insulating layer, and the first and second semiconductor, source and drain members; and
forming a pixel electrode connected to the first and the second drain members on the passivation layer,
wherein at least one pair of the first and the second gate members, the first and the second semiconductor members, the first and the second source members, and the first and the second drain members are formed using a divisional light exposure, and a boundary line between shots in the divisional light exposure is located between the first gate member and the second gate member, between the first semiconductor member and the second semiconductor member, between the first source member and the second source member, or between the first drain member and the second drain member.
2. The method of claim 1 , wherein the at least one pair has a shape symmetrical with respect to a predetermined line.
3. The method of claim 2 , wherein the predetermined line includes a boundary line between shots in light exposure.
4. The method of claim 1 , wherein the pair of first and second gate members, the pair of first and second semiconductor members, and the pair of first and second source members are connected to each other, respectively.
5. The method of claim 1 , wherein the first gate member, the first semiconductor member, the first source member, and the first drain member form a first thin film transistor, and the second gate member, the second semiconductor member, the second source member, and the second drain member form a second thin film transistor.
6. The method of claim 1 , wherein the first thin film transistor and the second thin film transistor are symmetrically aligned.
7. The method of claim 1 , wherein the first and the second thin film transistors are located opposite each other with respect to a boundary line between shots in light exposure.
8. The method of claim 1 , wherein channels of the first and the second thin film transistors have curved shapes.
9. The method of claim 1 , wherein the first and the second semiconductor members have substantially the same planar shapes as the first and the second source and drain members except for channel portions of the first and the second thin film transistors.