Granted Patent B2

US 8,301,905 · App. 11/517,641 · Granted Oct 30, 2012

Abstract

Claims (37)

1. A system comprising:

a controller; and

a processing element array coupled to the controller, wherein the processing element array is operative to perform one or more of encryption functions and decryption functions using an encryption algorithm, the processing element array comprising a matrix of processors, wherein the matrix of processors is configured in an N×M matrix of processors, where N is greater than one and M is greater than one,

each processor of the matrix comprising a multiplexor, wherein the multiplexor comprises a first input coupled to a first processor of the matrix, a second input coupled to a second processor of the matrix, a third input coupled to a third processor of the matrix, and a fourth input coupled to a fourth processor of the matrix;

wherein the processing element array comprises a matrix of processors operative to reduce side-channel attacks by generating noise, wherein the PE array is operative to perform operations that generate noise to distract or eliminate the ability of an agent from detecting information sensitive data, and wherein the noise comprises electrical and algorithmic noise.

2. The system of claim 1 wherein the processing element array is systolic.

3. The system of claim 1 wherein each processor of the matrix comprises an operations unit for performing one or more of encryption-related and decryption-related operations.

4. The system of claim 1 wherein the encryption algorithm is based at least in part on an Advanced Encryption Standard (AES) algorithm.

5. The system of claim 1 wherein the controller is a sequencer.

6. A method comprising:

providing a processing element array comprising a matrix of processors, wherein the matrix of processors is configured in an N×M matrix of processors, where N is greater than one and M is greater than one,

each processor of the matrix comprising a multiplexor, wherein the multiplexor comprises a first input coupled to a first processor of the matrix, a second input coupled to a second processor of the matrix, a third input coupled to a third processor of the matrix, and a fourth input coupled to a fourth processor of the matrix;

utilizing the processing element array to perform one or more of encryption functions and decryption functions using an encryption algorithm; and

causing the processors of the matrix to generate noise to reduce side-channel attacks;

wherein the processing element array comprises a matrix of processors operative to perform operations that generate noise to distract or eliminate the ability of an agent from detecting information sensitive data, and wherein the noise comprises electrical and algorithmic noise.

7. The method of claim 6 wherein the utilizing comprises performing cryptographic transformations on data.

8. The method of claim 7 wherein the cryptographic transformations performing comprises:

performing at least one sub-bytes transformation;

performing at least one shift-rows transformation;

performing at least one mix-columns transformation; and

performing at least one add-round-key transformation.

9. The method of claim 6 wherein the processing element array is systolic.

10. The method of claim 6 wherein the encryption algorithm is based at least in part on an Advanced Encryption Standard (AES) algorithm.

11. A computer-readable storage device containing program instructions for conserving power, the program instructions which when executed by a computer system cause the computer system to execute a method comprising:

providing a processing element array comprising a matrix of processors, wherein the matrix of processors is configured in an N×M matrix of processors, where N is greater than one and M is greater than one,

each processor of the matrix comprising a multiplexor, wherein the multiplexor comprises a first input coupled to a first processor of the matrix, a second input coupled to a second processor of the matrix, a third input coupled to a third processor of the matrix, and a fourth input coupled to a fourth processor of the matrix;

utilizing the processing element array to perform one or more of encryption functions and decryption functions using an encryption algorithm; and

causing the processors of the matrix to generate noise to reduce side-channel attacks;

wherein the processing element array comprises a matrix of processors operative to perform operations that generate noise to distract or eliminate the ability of an agent from detecting information sensitive data, and wherein the noise comprises electrical and algorithmic noise.

12. The computer-readable storage device of claim 11 wherein the utilizing comprises program instructions for performing cryptographic transformations on data.

13. The computer-readable storage device of claim 12 wherein the cryptographic transformations performing comprises program instructions for:

performing at least one sub-bytes transformation;

performing at least one shift-rows transformation;

performing at least one mix-columns transformation; and

performing at least one add-round-key transformation.

14. The computer-readable storage device of claim 11 wherein the processing element array is systolic.

15. The computer-readable storage device of claim 11 wherein the encryption algorithm is based at least in part on an Advanced Encryption Standard (AES) algorithm.

Assignments (7)