Ultra-wideband constant gain CMOS amplifier
View Patent ↗Circuitry and methods for improved amplifiers with large bandwidth and constant gain are provided. The combination of a synthetic inductive drain load and a bridged-T matching network provide amplifiers that can drive a substantial capacitive load with the above mentioned improvements over prior amplifiers. Additionally, circuits presented allow for improved rise time and insensitivity to temperature variations.
1. A system comprising:
a power source;
a first circuit for sourcing current from said power source and for providing a first current, wherein said first circuit comprises a transistor having a source terminal coupled to said power source;
a second circuit for receiving said first current, wherein said second circuit matches a reactance of a load so that the impedance of said second circuit is substantially the same as the impedance of said load, wherein said second circuit provides a second current; and
a third circuit for controlling said second current.
2. The system of claim 1 , wherein said second circuit comprises:
a first inductor;
a second inductor connected in a series configuration with said first inductor; and
a capacitor connected in parallel to said series configuration.
3. The system of claim 1 , wherein said source terminal of said transistor is coupled to a terminal of a resistor.
4. The system of claim 3 , wherein said resistor is a variable resistor.
5. The system of claim 3 , wherein said transistor is configured to have a substantially inductive impedance.
6. The system of claim 1 , wherein said first circuit comprises an inductor.
7. The system of claim 1 , wherein said second circuit comprises a broadband matching network.
8. The system of claim 7 , wherein said broadband matching network only matches part of said impedance of said load.
9. The method of claim 7 wherein said broadband matching network substantially matches said impedance of said load.
10. The system of claim 1 , wherein said second circuit comprises a bridged-T matching network.
11. The system of claim 2 , wherein said first inductor and said second inductor are connected to said load.
12. The system of claim 1 , wherein said third circuit is a transistor.
13. The system of claim 1 , wherein said third circuit controls said second current by drawing a third current from said second circuit, wherein a greater third current corresponds to a smaller second current.
14. The system of claim 13 , wherein said second current is greatest when said third current is substantially zero.
15. A system comprising:
a power source;
a first circuit for sourcing current from said power source and for providing a first current;
a second circuit for receiving said first current, wherein said second circuit matches a reactance of a load so that the impedance of said second circuit is substantially the same as the impedance of said load, wherein said second circuit provides a second current; and
a third circuit for controlling said second current, wherein said third circuit controls said second current by drawing a third current from said second circuit.
16. The system of claim 15 , wherein said second circuit comprises:
a first inductor;
a second inductor connected in a series configuration with said first inductor; and
a capacitor connected in parallel to said series configuration.
17. The system of claim 15 , wherein said first circuit comprises a transistor having a terminal coupled to said power source.
18. The system of claim 17 , wherein said transistor is configured to have a substantially inductive impedance.
19. The system of claim 15 , wherein said first circuit comprises an inductor.
20. The system of claim 15 , wherein said second circuit comprises a broadband matching network.
21. The system of claim 20 , wherein said broadband matching network only matches part of said impedance of said load.
22. The method of claim 20 , wherein said broadband matching network substantially matches said impedance of said load.
23. The system of claim 15 , wherein said second circuit comprises a bridged-T matching network.
24. The system of claim 15 , wherein said third circuit is a transistor.
25. The system of claim 15 , wherein said second current is greatest when said third current is substantially zero.