Semiconductor storage apparatus
View Patent ↗A semiconductor storage apparatus comprising: a ferroelectric memory; an SRAM 30 ; a counter 41 ; a CAM 10 that judges whether or not a block of data requested to be read out from the ferroelectric memory is stored in the SRAM 30 ; a storage control unit 51 that, if a result of the judgment is negative, performs a control to read out the requested block of data from the ferroelectric memory and stores a copy of the read-out block of data into a unit storage area in the SRAM 30 that corresponds to the count value indicated by the counter 41 ; and a counter control unit 52 that causes the counter 41 to update the count value each time a result of the judgment is negative.
1. A semiconductor storage apparatus comprising:
a ferroelectric memory including a plurality of unit storage areas that store data therein;
a cache memory including a plurality of unit storage areas each of which stores a copy of data stored in a unit storage area of the ferroelectric memory, and which are less in number than the plurality of unit storage areas included in the ferroelectric memory;
a counter operable to indicate a count value that corresponds to one of the plurality of unit storage areas in the cache memory;
a judging unit operable to judge whether or not a block of data requested to be read out from a unit storage area of the ferroelectric memory is stored in a unit storage area of the cache memory, as a copy of the block of data;
a storage control unit operable to, if a result of the judgment by the judging unit is negative, perform a control to read out the requested block of data from the ferroelectric memory and store a copy of the read-out block of data into a unit storage area in the cache memory that corresponds to the count value indicated by the counter; and
a counter control unit operable to cause the counter to update the count value each time a result of the judgment by the judging unit is negative.
2. The semiconductor storage apparatus of claim 1 , wherein
the cache memory has a longer life than the ferroelectric memory on a premise that a life of a memory is determined in accordance with a number of times data is read from the memory.
3. The semiconductor storage apparatus of claim 1 , wherein
the counter is an asynchronous counter.
4. A semiconductor storage apparatus comprising:
a ferroelectric memory including a plurality of unit storage areas that store data therein;
a cache memory including a plurality of unit storage areas each of which stores a copy of data stored in a unit storage area of the ferroelectric memory, and which are less in number than the plurality of unit storage areas included in the ferroelectric memory;
a storage control unit operable to perform a control to store a block of data, which is requested by a rewrite request to be written to the ferroelectric memory, into a unit storage area of the ferroelectric memory, and perform a control to store a copy of the requested block of data into a unit storage area of the cache memory; and
a judging unit operable to judge whether or not a block of data be replaced with the requested block of data is stored in a unit storage area of the cache memory as a copy thereof, wherein
if a result of the judgment by the judging unit is negative, the storage control unit does not perform a control to store a copy of the request block of data into a unit storage area of the cache memory.
5. A semiconductor storage apparatus comprising:
a ferroelectric memory including a plurality of unit storage areas that store data therein;
a cache memory including a plurality of unit storage areas each of which stores a copy of data stored in a unit storage area of the ferroelectric memory, and which are less in number than the plurality of unit storage areas included in the ferroelectric memory;
a storage control unit operable to perform a control to store a block of data, which is requested by a rewrite request to be written to the ferroelectric memory, into a unit storage area of the ferroelectric memory, and perform a control to store a copy of the requested block of data into a unit storage area of the cache memory;
a receiving unit operable to receive a specification of either a power-saving mode or a non-power-saving mode; and
a judging unit operable to judge whether or not a block of data to be replaced with the requested block of data is stored in a unit storage area of the cache memory as a copy thereof, wherein
if a result of the judgment by the judging unit is negative and the receiving unit receives specification of the power-saving mode, the storage control unit does not perform a control to store a copy of the requested block of data into a unit storage area of the cache memory.
6. A semiconductor storage apparatus comprising:
a ferroelectric memory including a plurality of unit storage areas that store data therein;
a cache memory including a plurality of unit storage areas each of which stores a copy of data stored in a unit storage area of the ferroelectric memory, and which are less in number than the plurality of unit storage areas included in the ferroelectric memory;
a storage control unit operable to perform a control to store a block of data, which is requested by a rewrite request to be written to the ferroelectric memory, into a unit storage area of the ferroelectric memory, and perform a control to store a copy of the requested block of data into a unit storage area of the cache memory;
a counter operable to indicate a count value that corresponds to one of the plurality of unit storage areas in the cache memory;
a judging unit operable to judge whether or not a block of data to be replaced with the requested block of data is stored in a unit storage area of the cache memory as a copy thereof; and
a counter control unit operable to cause the counter to update the count value each time a result of the judgment by the judging unit is negative, wherein
if a result of the judgment by the judging unit is positive, the storage control unit performs a control to replace, in the cache memory, the copy of the block of data to be replaced, with a copy of the requested block of data, and performs a control to replace the block of data stored in a unit storage area of the ferroelectric memory, with the requested block of data, and
if a result of the judgment by the judging unit is negative, the storage control unit performs a control to store a copy of the requested block of data into a unit storage area of the cache memory that corresponds to the count value indicated by the counter, and performs a control to replace the block of data stored in the unit storage area of the ferroelectric memory, with the requested block of data.
7. A semiconductor storage apparatus comprising:
a flash memory;
a ferroelectric memory that includes a plurality of unit storage areas in each of which a physical address of the flash memory and a logical address, which correspond to each other, are stored;
a cache memory that includes a plurality of unit storage areas in each of which a copy of a physical address of the flash memory and a copy of a logical address are stored with indication of correspondence therebetween, the cache memory including less unit storage areas in number than the ferroelectric memory;
a counter operable to indicate a count value that corresponds to one of the plurality of unit storage areas in the cache memory;
a judging unit operable to judge whether or not a copy of a logical address specified by a read request requesting to read data from the flash memory is stored in a unit storage area of the cache memory;
a storage control unit operable to, if a result of the judgment by the judging unit is negative, perform a control to read out a physical address corresponding to the logical address specified by the read request from the ferroelectric memory, read out the requested data from the flash memory using the read-out physical address, and store a copy of the logical address specified by the read request and a copy of the read-out physical address into a unit storage area in the cache memory that corresponds to the count value indicated by the counter, with indication of a correspondence between the copy of the logical address specified by the read request and the copy of the read-out physical address; and
a counter control unit operable to cause the counter to update the count value each time a result of the judgment by the judging unit is negative.
8. A semiconductor storage apparatus comprising:
a first memory that stores therein first-type data;
a second memory that includes a plurality of unit storage areas in each of which a piece of second-type data, which is used to read out a block of first-type data from the first memory, is stored;
a third memory that includes a plurality of unit storage areas in each of which a copy of a piece of second-type data is stored, the third memory including less unit storage areas in number than the second memory;
a judging unit operable to judge whether or not a copy of a piece of second-type data specified by a read request requesting to read data from the first memory is stored in a unit storage area of the third memory; and
a storage control unit operable to, if a result of the judgment by the judging unit is negative, perform a control to read out a piece of second-type data that is used to read out the requested block of first-type data, from the second memory, read out the requested block of first-type data from the first memory using the read-out piece of second-type data, and store a copy of the read-out piece of second-type data into a unit storage area in the third memory.
9. The semiconductor storage apparatus of claim 8 further comprising:
a counter operable to indicate a count value that corresponds to one of the plurality of unit storage areas in the third memory, wherein
the storage control unit operable to perform a control to store a copy of the read-out piece of second-type data into a unit storage area in the third memory that corresponds to the count value indicated by the counter.
10. The semiconductor storage apparatus of claim 9 , wherein
the second-type data is management data used to manage the first memory.
11. The semiconductor storage apparatus of claim 10 , wherein
the management data is address data of the first memory.
12. The semiconductor storage apparatus of claim 11 , wherein
each piece of the management data includes a physical address of the first memory and a logical address, which correspond to each other.
13. The semiconductor storage apparatus of claim 8 , wherein
the first memory is a flash memory,
the second memory is a ferroelectric memory, and
the third memory is a static random access memory.
14. A semiconductor storage apparatus comprising:
a first memory that stores therein first-type data;
a second memory that includes a plurality of unit storage areas in each of which a piece of second-type data, which is used to rewrite a block of first-type data stored in the first memory, is stored;
a third memory that includes a plurality of unit storage areas in each of which a copy of a piece of second-type data is stored, the third memory including less unit storage areas in number than the second memory;
a counter operable to indicate a count value that corresponds to one of the plurality of unit storage areas in the third memory;
a judging unit operable to judge whether or not a copy of a block of second-type data to be replaced with a block of second-type data as requested by a rewrite request, is stored in a unit storage area of the third memory; and
a storage control unit operable to, if a result of the judgment by the judging unit is positive, perform a control to replace the copy of the block of second-type data stored in a unit storage area of the third memory with a copy of the requested block of second-type data, and performs a control to replace the block of second-type data stored in a unit storage area of the second memory with the requested block of second-type data, and
if a result of the judgment by the judging unit is negative, perform a control to store a copy of the requested block of second-type data into a unit storage area of the third memory that corresponds to the count value indicated by the counter, and performs a control to replace the block of second-type data stored in a unit storage area of the second memory with the requested block of second-type data; and
a counter control unit operable to cause the counter to update the count value each time a result of the judgment by the judging unit is negative.
15. The semiconductor storage apparatus of claim 14 , wherein
the second-type data is management data used to manage the first memory.
16. The semiconductor storage apparatus of claim 15 , wherein
the management data is address data of the first memory.
17. The semiconductor storage apparatus of claim 16 , wherein
each piece of the management data includes a physical address and a logical address, which correspond to each other, of the first memory.
18. The semiconductor storage apparatus of claim 14 , wherein
the first memory is a flash memory,
the second memory is a ferroelectric memory, and
the third memory is a static random access memory.