Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator
View Patent ↗A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes converted by a conversion table. A plurality of ALUs perform the operation in accordance with the decoding result of the instruction decoder. Therefore, the number of instructions that can be executed in parallel per cycle may be increased while at the same time the capacity of the instruction memory is reduced.
1. A processor comprising:
an instruction memory for storing a plurality of instructions, each instruction including a first part as an instruction code and a second part that indicates a status of the instruction;
a converter for converting a packed instruction contained in the instruction code in the first part of the instruction fetched from the instruction memory into a plurality of instruction codes when the second part of the instruction indicates a first status;
a decoder for decoding the plurality of instruction codes converted by the converter when the second part of the instruction indicates the first status, and for decoding the instruction code in the first part of the instruction when the second part of the instruction indicates a second status; and
a plurality of operation units for operating each of the plurality of instruction codes in accordance with a decoding result of the decoder.
2. The processor according to claim 1 , wherein
the converter includes:
a plurality of flip-flops for storing a plurality of different sets of instruction codes; and
a selector for selecting a set of a plurality of instruction codes stored in the plurality of flip-flops in accordance with the packed instruction and outputting the selected set of the plurality of instruction codes to the decoder.
3. The processor according to claim 1 , wherein
the converter includes a memory for storing different sets of a plurality of instruction codes in respective areas, and selectively outputting a set of a plurality of instruction codes by using the packed instruction as an address.
4. The processor according to claim 1 , wherein
the converter is connected to a data bus connected with an external device, and a plurality of instruction codes are written by the external device through the data bus.
5. The processor according to claim 4 ,
wherein a set of a plurality of instruction codes determined as high in the frequency of occurrence by a compiler implemented by the external device is written in the converter.
6. The processor according to claim 1 , wherein
the converter is connected to a data bus of the processor, and a set of a plurality of instruction codes is written in the converter by the processor.
7. The processor according to claim 1 , further comprising an instruction queue interposed between the instruction memory and the converter.
8. The processor according to claim 1 , further comprising:
a selector for selectively outputting the plurality of instruction codes converted by the converter and the packed instruction to the decoder in accordance with a predetermined bit of the fetched instruction code.
9. The processor according to claim 8 , further comprising:
an instruction queue interposed between the selector and the decoder.
10. The processor according to claim 8 , wherein
the selector serially outputs the plurality of instruction codes converted by the converter to the decoder, and
the decoder decodes the plurality of instruction codes one by one and outputs a decoding result to a predetermined one of the plurality of operation units.
11. The processor according to claim 8 , wherein
the fetched instruction code contains information indicating whether a parallel or serial execution is carried out, and
the selector determines, in accordance with the information, whether the plurality of instruction codes are output to the decoder in parallel or serially.
12. The processor according to claim 8 , further comprising:
a jump destination instruction storage unit for storing a jump destination instruction; and
a holder for holding an address of the jump destination instruction, wherein
in the case where the decoder decodes a jump instruction free of penalty, the selector acquires the jump destination instruction held in the jump destination instruction storage unit, corresponding to the address of the jump destination instruction held in the holder and outputs the acquired jump destination instruction to the decoder.
13. The processor according to claim 1 , wherein
the converter converts only the operation code of the plurality of instruction codes, and
an operand of the plurality of instruction codes is included in the instruction code fetched from the instruction memory.