Heterogeneous integration of low noise amplifiers with power amplifiers or switches
View Patent ↗A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier having a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb), the substrate wafer having a first end and a second end, a conducting layer above the first end of the substrate wafer, an isolation implant providing lateral isolation in the conducting layer, a first active layer deposited above the conducting layer and configured for the low-noise amplifier, and a buffer layer deposited above the conducting layer and configured for the low-noise amplifier.
1. A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier comprising:
a substrate wafer suitable for high electron mobility transistors and having a first end and a second end;
an isolation implant separating the first end from the second end;
a pseudomorphic high electron mobility region deposited above the substrate wafer and configured for the power amplifier;
a first buffer layer deposited above the pseudomorphic high electron mobility region and configured for the low-noise amplifier; and
a first active layer deposited above the isolation implant and the first buffer layer, the first active layer configured for the low-noise amplifier.
2. The transistor of claim 1 , wherein the substrate wafer is selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb).
3. The transistor of claim 1 , wherein the pseudomorphic high electron mobility region comprises a second buffer layer and a second active layer.
4. The transistor of claim 1 , wherein the first active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer.
5. The transistor of claim 3 , wherein the second active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer.
6. The transistor of claim 1 further comprising metal contacts for the power amplifier or switch and the low-noise amplifier.
7. The transistor of claim 1 , wherein the first buffer layer is Aluminum Gallium Antimonide (AlGaSb).
8. A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier comprising:
a substrate wafer selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphide (InP) and Gallium Antimonide (GaSb), the substrate wafer having a first end and a second end;
a conducting layer above the first end of the substrate wafer;
an isolation implant providing lateral isolation in the conducting layer;
a first buffer layer deposited above the conducting layer and configured for the low-noise amplifier; and
a first active layer deposited above the conducting layer and above the first buffer layer, the first active layer configured for the low-noise amplifier.
9. The transistor of claim 8 , wherein the first active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer.
10. The transistor of claim 8 , wherein the conducting layer comprises a buffer layer and a second active layer.
11. The transistor of claim 8 , wherein the second active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer.
12. The transistor of claim 8 further comprising metal contacts for the low noise amplifier or switch on the second end of the substrate wafer and for the power amplifier on the first end of the substrate wafer.
13. The transistor of claim 8 , wherein the buffer layer is Aluminum Gallium Antimonide (AlGaSb).
14. A transistor heterogeneously integrating a power amplifier or switch with a low-noise amplifier comprising:
a substrate wafer suitable for high electron mobility transistors and having a first end and a second end;
a pseudomorphic high electron mobility region deposited above the substrate wafer and configured for the power amplifier;
an isolation implant above the second end of the substrate wafer, the isolation implant providing lateral isolation in the pseudomorphic high electron mobility region;
a first buffer layer deposited above the pseudomorphic high electron mobility region and the isolation implant, the first buffer layer configured for the low-noise amplifier; and
a first active layer deposited above the first buffer layer and the isolation implant, the first active layer configured for the low-noise amplifier.
15. The transistor of claim 14 , wherein the substrate wafer is selected from a group consisting of Gallium Arsenide (GaAs), Indium Phosphate (InP) and Gallium Antimonide (GaSb).
16. The transistor of claim 14 , wherein the pseudomorphic high electron mobility region comprises a second buffer layer and a second active layer.
17. The transistor of claim 16 , wherein the second active layer has an Indium Gallium Arsenide (InGaAs) channel layer and an Aluminum Gallium Arsenide (AlGaAs) barrier layer.
18. The transistor of claim 14 , wherein the first active layer has an Indium Arsenide (InAs) channel layer and an Aluminum Antimonide (AlSb) barrier layer.
19. The transistor of claim 14 further comprising metal contacts for the power amplifier or switch and the low-noise amplifier.