Gate driving circuit and display device having the same

1. A gate driving circuit for outputting driving signals to a plurality of gate lines, the circuit comprising:

p shift registers for driving gate lines divided into p groups, respectively, wherein the plurality of gate lines comprises first to p-th gate lines sequentially deposited and corresponding to first to p-th shift registers, respectively,

wherein each of the p shift registers includes a plurality of stages dependently connected to one another, and each of p start signals is sequentially input to an input terminal of a first stage of each of the first to p-th shift registers, respectively, and an output signal from a selected stage is connected to an input terminal of the next stage of each of the p shift registers, whereby the first to p-th gate lines are sequentially driven by means of the output signals of first to p-th stages corresponding to the first to p-th shift registers, respectively,

wherein each of the p start signals of a high state are partially overlapped,

wherein the p start signals used in the p shift registers are shifted from one another by 1/p, and

wherein p is a natural number of four, and the gate lines are divided into four groups in an order of 4n-3, 4n-2, 4n-1 and 4n, wherein n is a natural number of one or more.

2. The gate driving circuit as claimed in claim 1 , wherein each of the plurality of stages comprises:

an input terminal for receiving a stage driving signal output from any one stage of the previous stages;

a clock terminal for receiving any one clock signal of a plurality of clock signals with phases different from one another;

a control terminal for receiving a stage driving signal output from any one stage of the next stages;

a first output terminal for outputting a gate driving signal.

3. The gate driving circuit as claimed in claim 2 further comprising a second output terminal for outputting the stage driving signal to any one stage of the next stages.

4. The gate driving circuit as claimed in claim 1 , wherein each of the plurality of stages comprises:

an input terminal for receiving a stage driving signal output from any one stage of the previous stages;

a clock terminal for receiving any one clock signal of a plurality of clock signals with phases different from one another;

a control terminal for receiving a stage driving signal output from any one stage of the next stages;

a first output terminal for outputting a gate driving signal.

5. The gate driving circuit as claimed in claim 4 further comprising a second output terminal for outputting the stage driving signal to any one stage of the next stages.

6. A display device, comprising:

a display device including a plurality of gate lines, a plurality of data lines crossing the gate lines, and a switching element and a pixel electrode formed between the gate and data lines;

a gate driving circuit for selecting a gate line and allowing a switching element connected to the selected gate line to be switched on; and

a source driving circuit for driving a data line connected to the pixel electrode by means of the switching on of the switching element in accordance with input image data,

wherein the gate driving circuit includes p shift registers for driving the gate lines divided into p groups, respectively, wherein the plurality of gate lines comprises first to p-th gate lines sequentially deposited and corresponding to first to p-th shift registers, respectively, each of the shift registers includes a plurality of stages dependently connected to one another, and each of first to p-th start signals is sequentially input to an input terminal of a first stage of each of the first to p-th shift registers, respectively, and an output signal from a selected stage is connected to an input terminal of the next stage of each shift register, whereby the first to p-th gate lines are sequentially driven by the output signals of first to p-th stages, corresponding to the first to p-th shift registers, respectively, and

wherein each of the p start signals of a high state are partially overlapped,

wherein the p start signals used in the p shift registers are shifted from one another by 1/p, and

wherein p is a natural number of four, and the plurality of gate lines are divided into four groups in an order of 4n-3, 4n-2, 4n-1 and 4n,

wherein n is a natural number of one or more.

7. The display device as claimed in claim 6 , wherein each of the plurality of stages comprises:

an input terminal for receiving a stage driving signal output from any one stage of the previous stages;

a clock terminal for receiving any one clock signal of a plurality of clock signals with phases different from one another;

a control terminal for receiving a stage driving signal output from any one stage of the next stages;

a first output terminal for outputting a gate driving signal.

8. The display device as claimed in claim 7 further comprising a second output terminal for outputting the stage driving signal to any one stage of the next stages.

9. The display device as claimed in claim 6 , wherein each of the plurality of stages comprises:

an input terminal for receiving a stage driving signal output from any one stage of the previous stages;

a clock terminal for receiving any one clock signal of a plurality of clock signals with phases different from one another;

a control terminal for receiving a stage driving signal output from any one stage of the next stages;

a first output terminal for outputting a gate driving signal.

10. The display device as claimed in claim 9 further comprising a second output terminal for outputting the stage driving signal to any one stage of the next stages.

11. The display device as claimed in claim 6 , wherein the source driving circuit applies a data voltage for the last period among p periods obtained by dividing a period when the gate driving signal is applied to the gate line by p.