Circuitry and method to detect conditions of data

1. A condition detection system comprising:

change circuitry configured to detect a change in at least one predetermined bit of an N-bit bus, where N is a positive integer, and to provide a corresponding change signal indicative of the detected condition;

match circuitry configured to detect a match condition for up to a selected subset of predetermined bits of the N-bit bus and to provide a corresponding match signal indicative of the detected condition; and

selection circuitry programmable to provide a selected one of the change signal and the match signal as a corresponding output signal.

2. The system of claim 1 , further comprising a counter configured to adjust a count value based on the corresponding output signal.

3. The system of claim 1 , further comprising a logic analyzer configured to at least one of (i) qualify storage of data on the N-bit bus and (ii) trigger logic analysis of data on the N-bit bus in response to the corresponding output signal.

4. The system of claim 1 , further comprising at least one other detection circuit configured to detect a condition of at least one bit on the N-bit bus other than the change and the match condition and provide a corresponding detector signal indicative thereof the detected condition, the selection circuitry being programmable to provide the corresponding output signal by selecting one of the change signal, the match signal and the detector signal.

5. The system of claim 1 , further comprising a data storage device configured to store a logic signal indicative of the whether the change circuitry detected the change in the at least one predetermined bit of the N-bit bus, the data storage device providing the change signal to an input of the selection circuitry.

6. The system of claim 1 , wherein the match logic circuitry further comprises a match mode selector configured to select a subset of the N-bit bus to which the match condition is applied.

7. The system of claim 1 , wherein the change circuitry further comprises an input for receiving change mask data to program the at least one predetermined bit of the N-bit bus.

8. The system of claim 7 , further comprising data storage that stores N-bits of data from the N-bit bus corresponding to a previous state of the N-bits of data, the change logic circuitry configured to detect the change in the at least one predetermined bit of the N-bit bus as a function of the stored N-bit of data and a present N-bits of data from the N-bit bus.

9. The system of claim 1 , wherein the match logic circuitry further comprises an input for receiving match mask data to program the match condition for up to a selected N/2 predetermined bits of the N-bit bus.

10. The system of claim 9 , wherein the change logic circuitry further comprises an input for receiving change mask data to program the at least one predetermined bit of the N-bit bus.

11. The system of claim 10 , wherein at least a substantial portion of bits in the change mask data and the match mask data are the same.

12. Circuitry for analyzing multi-bit data that propagates over a bus, comprising:

means for performing a plurality of detection functions, each of the plurality of detection functions being operative to detect a respective condition of a selected portion of the multi-bit data and for providing a corresponding logic signal indicative of whether the respective condition has been met, the plurality of detection functions comprising:

at least means for detecting a change in the multi-bit data; and ,

means for detecting a match condition in at least a selected portion of the multi-bit data; and

means for selecting the corresponding logic signal and for providing the selected signal as an output signal based on a mode control signal.

13. The circuitry of claim 12 , further comprising:

means for qualifying storage of data on the N-bit bus based on the output signal; and

means for triggering logic analysis of data on the N-bit bus based on the output signal.

14. The circuitry of claim 12 , wherein the plurality of detection functions further comprises means for performing at least one of a bit-wise AND function and a bit-wise OR function for at least one bit on the N-bit bus and for providing a corresponding AND/OR logic signal.

15. The circuitry of claim 12 , wherein the means for performing a plurality of detection functions further comprises means for programming mask data to set the selected portion of the multi-bit data.

16. The circuitry of claim 15 , wherein at least a substantial portion of the mask data is shared by at least some of the plurality of detection functions.

17. A method for analyzing data propagating on an N-bit bus, where N is a positive integer, the method comprising:

asserting a logic change signal if a predetermined portion of the data changes;

asserting a logic match signal if a predetermined portion of the data includes a specified bit pattern;

providing an output signal that includes one of the logic change signal and the logic match signal according to an operating mode.

18. The method of claim 17 further comprising:

programming change mask data to define a first predetermined portion of the data, the logic change signal being asserted if the first predetermined portion of the data changes; and

programming match mask data to define a second predetermined portion of the data, the logic match signal being asserted if the second predetermined portion of the data includes the specified bit pattern.

19. The method of claim 18 , wherein the change mask data and the match mask data are the same.

20. The method of claim 19 , further comprising setting the operating mode based on a mode control signal, the output signal corresponding to one of the logic change signal or the logic match signal as selected based on the mode control signal.