Integrated circuit bipolar transistor

1. A method for manufacturing a bipolar transistor, the method comprising:

coating a semiconductor substrate that includes a collector region with a layer of a first insulator and with a polysilicon layer;

forming an opening extending through the polysilicon layer and extending only partially through the first insulator layer thereby eliminating at least a surface portion of the first insulator layer exposed by the opening;

surrounding exposed surfaces of the polysilicon layer with a layer of a second insulator after forming an opening extending through the polysilicon layer and extending only partially through the first insulator layer, the lateral portions of the second insulator layer in the opening forming a spacer that has a lower spacer surface that is deeper than a lower surface of the polysilicon layer;

eliminating a portion of the first insulator layer including the portion of the first insulator layer located beneath the opening and portions laterally beyond said opening thereby leaving in overhanging position a portion of the polysilicon layer;

growing by selective epitaxy a base semiconductor layer on the collector region so that the base layer rises partially back along a substantially vertical central portion beyond the lower spacer surface in the opening of the first insulator layer in an installation under vacuum after formation of the spacer having the lower spacer surface that is deeper than the lower surface of the polysilicon layer; and

depositing an emitter semiconductor layer under vacuum in the same installation with the vacuum maintained between the growth of the base semiconductor layer and the deposition of the emitter semiconductor layer.

2. The method of claim 1 , wherein growing by selective epitaxy a base semiconductor layer comprises:

growing a heavily carbon doped silicon-germanium layer; and

growing a silicon layer that is at most lightly doped.

3. A method for manufacturing a bipolar transistor, the method comprising:

forming an opening extending through a polysilicon layer and extending only partially through a layer of a first insulator, thereby eliminating at least a surface portion of the layer of the first insulator, where the polysilicon layer at least partially overlays the layer of the first insulator that is on a substrate;

forming a layer of a second insulator that covers exposed surfaces of the polysilicon layer at least in the opening such that a lower surface of the second insulator layer is deeper than a lower surface of the polysilicon layer, after forming an opening extending through a polysilicon layer and extending only partially through a layer of a first insulator;

eliminating a portion of the layer of the first insulator located under the opening and eliminating adjacent portions of the layer of the first insulator such that portions of a bottom surface of the polysilicon layer are exposed, forming an open space in the layer of the first insulator;

growing a base semiconductor layer by selective epitaxy in the open space on the substrate such that the base layer within the opening extends higher than the lower surface of the layer of the second insulator, after forming a laser of a second insulator that covers exposed surfaces of the polysilicon layer at least in the opening such that a lower surface of the second insulator layer is deeper than a lower surface of the polysilicon layer; and

depositing an emitter semiconductor layer, wherein no insulating elements are formed between commencing growing of the base semiconductor layer and commencing depositing the semiconductor layer,

4. The method of claim 3 , further comprising:

depositing a first insulator layer on a semiconductor substrate; and

depositing a polysilicon layer on the first insulator layer on the semiconductor substrate before forming the opening.

5. The method of claim 3 , wherein the base semiconductor layer is grown under vacuum, the emitter semiconductor layer is deposited under vacuum, and the vacuum is maintained between the growth of the base semiconductor layer and the deposition of the emitter semiconductor layer.

6. The method of claim 3 , wherein forming a layer of a second insulator tat covers exposed surfaces of the polysilicon layer comprises:

depositing a layer of a second insulator over the polysilicon layer and the opening; and

etching the layer of the second insulator exposing an upper surface of the layer of the first insulator in the opening.

7. The method of claim 3 , further comprising:

forming a first layer of a second insulator on the polysilicon layer before forming the opening; wherein forming the opening comprises forming the opening extending through the first layer of the second insulator, through the polysilicon layer and into the layer of the first insulator, and wherein the layer of the second insulator that covers exposed surfaces of the polysilicon layer is a second layer of the second insulator.

8. The method of claim 3 , wherein a difference in depth between the lower surface of the second insulator layer and the lower surface of the polysilicon layer is between about 10 nm and about 20 nm.

9. The method of claim 3 , wherein the lower surface of the second insulator layer is deeper than an upper surface of the layer of the first insulator.

10. The method of claim 3 , wherein the base semiconductor layer comprises carbon-doped SiGe.

11. The method of claim 10 , wherein the emitter layer comprises an N-doped semiconductor.

12. The method of claim 3 , wherein depositing an emitter semiconductor layer comprises epitaxially growing an undoped silicon layer.

13. The method of claim 3 , wherein a width of the base layer in the opening is about 100 nm.

14. The method of claim 3 , wherein a lateral top surface of the base layer contacts the polysilicon layer over a region with a width of about 50 nm.

15. The method of claim 3 , wherein the first insulator comprises silicon oxide.

16. The method of claim 3 , wherein the layer of the first insulator has a thickness measuring between about 20 nm and about 30 nm.

17. The method of claim 3 , wherein the second insulator comprises silicon oxynitride.

18. The method of claim 3 , wherein the second insulator comprises silicon nitride.

19. The method of claim 3 , wherein the layer of the second insulator is about 50 nm thick.

20. The method of claim 3 , wherein the polysilicon layer comprises heavily doped P-type polysilicon.