Memory with a refresh portion for rewriting data

1. A memory comprising:

a memory cell array including a plurality of memory cell blocks each having a plurality of nonvolatile memory cells;

a first frequency detecting portion detecting access frequencies with respect to said plurality of memory cell blocks respectively;

a comparator comparing said access frequencies with respect to said plurality of memory cell blocks detected by said first frequency detecting portion with each other; and

a refresh portion exercising control for selecting a memory cell block from among said plurality of memory cell blocks on the basis of comparison data output from said comparator and preferentially rewriting data in said memory cells included in said selected memory cell block.

2. The memory according to claim 1 , wherein

said comparator detects a memory cell block exhibiting the maximum access frequency among said plurality of memory cell blocks, and

said refresh portion exercises control for preferentially rewriting data in said memory cells included in said memory cell block exhibiting the maximum access frequency.

3. The memory according to claim 1 , wherein

said comparator detects the sequence of the access frequencies with respect to said plurality of memory cell blocks, and

said refresh portion exercises control for selecting said memory cell block from among said plurality of memory cell blocks on the basis of sequence data output from said comparator and rewriting data in said memory cells included in said selected memory cell block.

4. The memory according to claim 1 , wherein

said refresh portion rewrites data in parallel with an access operation.

5. The memory according to claim 4 , wherein

said refresh portion exercises control for preferentially rewriting data in said memory cells included in a memory cell block exhibiting the maximum access frequency among said memory cell blocks, included in said plurality of memory cell blocks, other than a memory cell block subjected to said access operation.

6. The memory according to claim 5 , wherein

said refresh portion exercises control for rewriting data in said memory cells included in said memory cell block exhibiting the second maximum access frequency among said plurality of memory cell blocks when said access operation is performed on said memory cell block exhibiting the maximum access frequency among said plurality of memory cell blocks.

7. The memory according to claim 1 , wherein

said refresh portion rewrites data in a period including no access operation.

8. The memory according to claim 1 , wherein

said refresh portion rewrites data simultaneously with an access operation in a cycle period.

9. The memory according to claim 1 , wherein

said refresh portion selects said selected memory cell block, to be subjected to a rewrite-operation controlled by said refresh portion on the basis of said comparison data output from said comparator every period for performing a rewrite operation controlled by said refresh portion.

10. The memory according to claim 1 , wherein

said refresh portion exercises control for continually rewriting data in said selected memory cell block until completely rewriting data in all said memory cells included in said selected memory cell block.

11. The memory according to claim 1 , further comprising a second frequency detecting portion detecting access frequencies with respect to all said memory cells provided in said memory cell array, wherein

said refresh portion exercises control for selecting said selected memory cell block from among said plurality of memory cell blocks on the basis of said comparison data output from said comparator and preferentially rewriting data in said memory cells included in said selected memory cell block when said second frequency detecting portion detects that the total access frequency with respect to all memory cells has reached a prescribed number of times.

12. The memory according to claim 11 , further comprising:

a plurality of word lines each connected with a prescribed number of said memory cells, and

a holding portion holding presence/absence of an access operation every said prescribed number of memory cells connected to each of said plurality of word lines, wherein

said refresh portion exercises control for selecting said selected memory cell block from among said plurality of memory cell blocks on the basis of said comparison data output from said comparator and data held in said holding portion and rewriting data in said memory cells included in said selected memory cell block when said second frequency detecting portion detects that the total access frequency with respect to all said memory cells has reached said prescribed number of times.

13. The memory according to claim 12 , wherein

said refresh portion exercises control for rewriting no data in said memory cells included in said selected memory cell block when said selected memory cell block is accessed through all said word lines included in said selected memory cell block.

14. The memory according to claim 1 , wherein

said refresh portion exercises control for preferentially rewriting data in said memory cells included in said selected memory cell block when the access frequency with respect to said selected memory cell block has reached a prescribed number of times.

15. The memory according to claim 1 , further comprising a plurality of word lines each connected with a prescribed number of said memory cells, wherein

said refresh portion exercises control for rewriting data in said plurality of memory cells linked to a single one of said word lines with respect to said memory cells included in said selected memory cell block.

16. The memory according to claim 15 , further comprising a storage portion storing the range of said word lines of said memory cell blocks subjected to rewrite operations.

17. The memory according to claim 1 , wherein

said memory cells include ferroelectric capacitors having ferroelectric films.