Non-volatile reprogrammable memory

1. A non-volatile memory point comprising:

a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, wherein:

at least the main part of the active portions has a P-type doping and the inactive portions comprise at least one N-type doped area forming a portion of a PN junction;

first and second wells of a first doping type are placed in an upper portion of the substrate of a second doping type;

the floating gate comprises a ring-shaped active portion placed above the first well, a non-active portion placed above an insulating area placed in the upper portion of the substrate between the first and second wells, and an active end portion placed above the second well; and

drain and source areas of the second doping type are placed at the surface of the first well respectively inside and outside, in top view, of the active ring-shaped portion.

2. The memory point of claim 1 , wherein the thick insulating layers are placed in the upper portion of the substrate and insulate a plurality of wells formed in the semiconductor substrate.

3. The memory point of claim 1 , further comprising means for electron transfer from said N-type doped area, forming a well of storage of electrons injected into the floating gate in a programming operation, towards all or part of the active portions.

4. The memory point of claim 3 , wherein said transfer means comprise at least one coupling electrode placed close to said at least one N-type doped area and separated therefrom by an insulating portion, said at least one coupling electrode being connected to a biasing electrode.

5. The memory point of claim 1 , wherein the ring-shaped active portion and the end active portion are P-type doped and the inactive portion is N-type doped.

6. The memory point of claim 1 , wherein the ring-shaped active portion and the end active portion are P-type doped, and the inactive portion comprises several N-type doped areas separated from one another by P-type doped areas.

7. The memory point of claim 1 , wherein the ring-shaped active portion and the end active portion are P-type doped, the inactive portion comprising a P-type doped rectilinear portion exhibiting lateral prominences having N-type doped ends.

8. The memory point of claim 1 , comprising electrode areas placed close to the inactive portion and exhibiting prominences placed close to the N-type doped areas.

9. A non-volatile memory cell comprising:

a substrate;

a first transistor formed in the substrate; and

a second transistor formed in the substrate, the first and second transistors including a common floating gate comprising a first active portion associated with the first transistor and insulated from the substrate by a thin insulating layer, a second active portion associated with the second transistor and insulated from the substrate by a thin insulating layer, and an intermediate portion insulated from the substrate by a thick insulating layer, the floating gate including at least one PN junction, wherein the thick insulating layer is formed in an upper portion of the substrate and insulates wells associated with the first and second transistors.

10. The non-volatile memory cell as defined in claim 9 , wherein each of the first and second active portions has a P-type doped area and the intermediate portion includes at least one N-type doped area.

11. The non-volatile memory cell as defined in claim 9 , further comprising at least one electrode to enhance transfer of electrons from the intermediate portion to the first and second active portions of the floating gate.

12. The non-volatile memory cell as defined in claim 9 , further comprising at least one coupling electrode placed close to the intermediate portion and separated therefrom by an insulating portion, to enhance transfer of electrons from the intermediate portion to the first and second active portions of the floating gate.

13. A non-volatile memory cell comprising:

a substrate;

a first transistor formed in the substrate;

a second transistor formed in the substrate, the first and second transistors including a common floating gate comprising a first active portion associated with the first transistor and insulated from the substrate by a thin insulating layer, a second active portion associated with the second transistor and insulated from the substrate by a thin insulating layer, and an intermediate portion insulated from the substrate by a thick insulating layer, the floating gate including at least one PN junction; and

first and second wells of a first doping type in the upper portion of the substrate under the first and second transistors, respectively, the first active portion comprising a ring-shaped active portion above the first well, drain and source areas of the first transistor being placed at the surface of the first well inside and outside, respectively, of the ring-shaped active portion.

14. The non-volatile memory cell as defined in claim 13 , wherein the intermediate portion is placed above the thick insulating layer between the first and second wells, and the second active portion is placed above the second well.

15. The memory cell as defined in claim 14 , wherein the ring-shaped active portion and the second active portion are P-type doped and the intermediate portion is N-type doped.

16. The memory cell as defined in claim 14 , wherein the ring-shaped active portion and the second active portion are P-type doped areas, and the intermediate portion comprises N-type doped areas and P-type doped areas forming two or more PN junctions.

17. The memory cell as defined in claim 16 , further comprising at least one coupling electrode adjacent to the intermediate portion and having projections in close proximity to the N-type doped areas.

18. The memory cell as defined in claim 14 , wherein the ring-shaped active portion and the second active portion are P-type doped areas, and the intermediate portion comprises a P-type doped central area having lateral projections with N-type doped ends.

19. The memory cell as defined in claim 18 , further comprising at least one coupling electrode adjacent to the intermediate portion of the floating gate and having projections in close proximity to the N-type doped ends.