Circuit for biasing a transistor and related system and method
View Patent ↗An embodiment of a circuit for biasing a transistor such as an amplifier transistor includes reference and bias nodes, and includes buffer, reference, and feedback stages. The reference node receives a reference current, and the bias node, which is for coupling to the transistor, carries a bias signal. The buffer stage buffers the reference node from the bias node. The reference stage generates the bias signal from the reference current, and the bias signal causes the transistor to conduct a bias current that is proportional to the reference current. And the feedback stage is coupled between the reference and bias nodes. As compared to known bias circuits, such a bias circuit may reduce the amplitude and duration of a transient overshoot in the bias current of a field-effect transistor when the DC component of the transistor's drain voltage transitions from one value to another value. Such a bias circuit may also reduce the difference between the values of the bias current through the transistor for different supply voltages. And such a bias circuit may reduce the difference between the predicted and actual values of the bias current through the transistor for a given input voltage such as that between the gate and the source of a field-effect transistor.
1. A circuit for biasing an amplifier transistor, the circuit comprising:
a reference node operable to receive a reference current;
a bias node operable to be coupled to the transistor and to carry a bias signal;
first, second, third, and fourth supply nodes, the amplifier transistor operable to be coupled to the first supply node;
a current source coupled between the second supply node and the reference node and operable to generate the reference current;
a buffer stage having a buffer input terminal coupled to the reference node and having a buffer output terminal coupled to the bias node, wherein the buffer stage comprises a buffer transistor having a first terminal coupled to the third supply node, a second terminal coupled to the buffer output terminal, and a control terminal coupled to the buffer input terminal;
a reference stage coupled to the reference and bias nodes and operable to generate the bias signal from the reference current, the bias signal operable to cause the transistor to conduct a bias current that is proportional to the reference current, wherein the reference stage comprises,
a reference transistor having a first terminal coupled to the reference node, a second terminal coupled to the fourth supply node, and a control terminal, and
a first impedance element serially coupled between the bias node and the fourth supply node; and
wherein the feed back stage comprises,
a feedback transistor having a first terminal coupled to the first supply node, a second terminal, and a control terminal coupled to the reference node,
a second impedance element coupled between the second terminal of the feedback transistor and the fourth supply node,
a third impedance element coupled between the second terminal of the feedback transistor and the control terminal of the reference transistor, and
a fourth impedance element coupled between the control terminal of the reference transistor and the bias node.
2. The circuit of claim 1 , wherein the reference transistor is a reference field-effect transistor.
3. The circuit of claim 1 , wherein the current source comprises a first resistive element coupled between the second supply node and the reference node and operable to conduct the reference current;
wherein the first impedance is a second resistive element,
wherein the second impedance is a third resistive element,
wherein the third impedance is a fourth resistive element, and
wherein the fourth impedance is a fifth resistive element.
4. The circuit of claim 1 , further comprising a sense element that is operable to:
sense a change in the bias current through the amplifier transistor; and
cause the reference stage to oppose the change in the bias current by adjusting the bias signal.
5. The circuit of claim 1 , wherein the feedback transistor is operable to cause the reference transistor to oppose a change in the bias signal.
6. The circuit of claim 1 , wherein at least one of the first, second, third, and fourth supply nodes is the same as another one of the first, second, third, and fourth supply nodes.