Nonvolatile semiconductor memory device
View Patent ↗A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.
1. A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate, comprising a plurality of MOS transistors sharing the floating gate,
wherein the MOS transistors include:
a first MOS transistor formed in an n-well region, one of a source and a drain of the first MOS transistor being formed by a p-type diffusion layer; and
a second MOS transistor formed in an n-well region, one of a source and a drain of the second MOS transistor being formed by an n-type diffusion layer.
2. The nonvolatile semiconductor memory device of claim 1 , wherein the second MOS transistor is a depletion MOS transistor.
3. The nonvolatile semiconductor memory device of claim 2 , wherein the second MOS transistor and the first MOS transistor have a gate area ratio of substantially 1:9.
4. The nonvolatile semiconductor memory device of claim 1 , wherein the MOS transistors further include a third MOS transistor sharing the floating gate, and
data read operation is performed using a current value of the third MOS transistor.
5. The nonvolatile semiconductor memory device of claim 4 , wherein the second MOS transistor and the third MOS transistor have a gate area ratio of substantially 1:2 to 4.
6. The nonvolatile semiconductor memory device of claim 4 , wherein the third MOS transistor and the first MOS transistor have a gate area ratio of substantially 1:2 to 4.
7. The nonvolatile semiconductor memory device of claim 4 , wherein the second MOS transistor, the third MOS transistor and the first MOS transistor have a gate area ratio of substantially 1:3:9.
8. A nonvolatile semiconductor memory device formed by modifying the nonvolatile semiconductor memory device of claim 4 into a differential cell structure, wherein drains of the third MOS transistors in a first bit cell and a second bit cell are connected to inputs of a differential amplifier.
9. The nonvolatile semiconductor memory device of claim 4 , wherein the first, second and third MOS transistors have a gate-oxide-film thickness substantially equal to that of a MOS transistor forming an input/output circuit of LSI.
10. The nonvolatile semiconductor memory device of claim 4 , wherein the first, second and third MOS transistors have a gate-oxide-film thickness ranging from 7 nm to 8 nm.
11. The nonvolatile semiconductor memory device of claim 1 , wherein a first bias is applied to one of a p-type source and a p-type drain of the first MOS transistor and one of an n-type source and an n-type drain of the second MOS transistor for writing,
a second bias is applied to one of a p-type source and a p-type drain of the first MOS transistor for erasure, and
the first bias is higher than the second bias.
12. The nonvolatile semiconductor memory device of claim 11 , wherein the first bias is in the range from 7V to 10V.
13. The nonvolatile semiconductor memory device of claim 11 , wherein the second bias is substantially equal to a power supply voltage of a logic circuit of LSI.
14. A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate, the nonvolatile semiconductor memory device comprising a plurality of MOS transistors sharing the floating gate,
wherein the MOS transistors include:
a first MOS transistor formed in an n-well region, one of a source and a drain of the first MOS transistor being formed by a p-type diffusion layer;
a second MOS transistor formed in an n-well region, one of a source and a drain of the second MOS transistor being formed by a p-type diffusion layer;
a third MOS transistor formed in an n-well region, one of a source and a drain of the third MOS transistor being formed by an n-type diffusion layer; and
a fourth MOS transistor formed by an NMOS.
15. The nonvolatile semiconductor memory device of claim 14 , wherein a first bias is applied to the n-well regions of the first and second MOS transistors for write operation,
a second bias is applied to the n-well region of the second MOS transistor for read operation,
a third bias is applied to the n-well region of the third MOS transistor for erase operation, and
each of the first and third biases is higher than the second bias.
16. A nonvolatile semiconductor memory device formed by modifying the nonvolatile semiconductor memory device of claim 14 into a differential cell structure, wherein drains of the fourth MOS transistors in a first bit cell and a second bit cell are connected to inputs of a differential amplifier.
17. The nonvolatile semiconductor memory device of claim 14 , wherein the first, second, third and fourth MOS transistors have a gate-oxide-film thickness substantially equal to that of a MOS transistor forming an input/output circuit of LSI.