Method and system for providing information for recovering a clock frequency
View Patent ↗A method and a system for providing information for recovering a clock frequency via a data network comprise generating a value representative of a frequency difference between a clock frequency and a reference frequency by using a digital phase-locked loop at an ingress interface of a data network, transmitting the generated value over the data network, and recovering the clock frequency at an egress interface of the data network by using the reference frequency and the transmitted value. Other systems and methods are also disclosed.
1. A system, comprising:
a time domain multiplexing (TDM) transmission entity comprising: a first TDM transmission system to transmit a TDM bitstream over a T-carrier or E-carrier line according to a TDM service clock, a first TDM reception system to receive the TDM bitstream over the T-carrier or E-carrier line according to the TDM service clock, and a digital phase-locked loop to generate a digital value representative of a frequency difference between the TDM service clock frequency and a reference frequency; and
a first interworking function element to convert the TDM bitstream to a series of packets and transmit the series of packets over an asynchronous network along with the generated digital value according to the reference frequency.
2. The system of claim 1 , further comprising:
a TDM reception entity coupled to the first interworking function element via the asynchronous network, the TDM reception entity comprising: a second interworking function element to receive the series of packets and extract the digital value therefrom, a frequency synthesizer to recover the TDM service clock from the extracted digital value and the reference frequency, wherein the second interworking function element is configured to recover the TDM bitstream based on the series of packets and the TDM service clock.
3. The system of claim 1 , wherein the asynchronous network comprises a packet-switched network.
4. The system of claim 1 , wherein the asynchronous network comprises a gigabit passive optical network (GBON).
5. The system of claim 1 , wherein the digital phase-locked loop comprises a proportional-integral control loop or a proportional-integral-differential control loop, and wherein the transmitted digital value corresponds an integral term of the proportional-integral control loop or the proportional-integral-differential control loop.
6. The system of claim 1 , wherein the digital phase-locked loop (PLL) comprises an integral part having an input coupled to an input of the digital PLL and an output coupled to a first input of a first adder; a control loop to couple an output of the first adder to a second input of the first adder; a proportional part having an input coupled to the input of the PLL and having an output coupled to a first input of a second adder; the second adder having a second input coupled to the output of the first adder.