IP Library Granted Patent US 7,696,779
Granted Patent B2
US 7,696,779 · App. 11/526,816 · Granted Apr 13, 2010

System LSI

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Quick Facts
Patent No.
US 7,696,779
App. No.
11/526,816
Granted
Apr 13, 2010
Kind
B2
Abstract

A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Claims (20)

1. A system LSI, comprising an input/output section and a logic circuit section,

wherein the input/output section includes:

an I/O power source cell having a power supply voltage higher than a power source for the logic circuit section; and

a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell, and

the logic circuit section includes:

a first I/O power consuming circuit which uses the I/O power source cell as a power source, the first I/O power consuming circuit being connected to a first line leading from the I/O power source line in at least one of the plurality of I/O cells,

wherein the plurality of I/O cells includes first and second I/O cells each of which has a pad connected to an external terminal, said system LSI further comprising:

a filler cell which is provided between the first I/O cell and the second I/O cell and in which the I/O power source line is provided,

wherein the first I/O power consuming circuit is provided in a layer below the filler cell, and

the first I/O power consuming circuit is connected to the I/O power source line in the filler cell.

2. A system LSI, comprising an input/output section and a logic circuit section,

wherein the input/output section includes:

an I/O power source cell having a power supply voltage higher than a power source for the logic circuit section; and

a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell, and

the logic circuit section includes:

a first I/O power consuming circuit which uses the I/O power source cell as a power source, the first I/O power consuming circuit being connected to a first line leading from the I/O power source line in at least one of the plurality of I/O cells,

wherein the plurality of I/O cells includes an I/O cell which includes a pad connected to an external terminal,

the first I/O power consuming circuit is provided in a layer below the pad, and

the first I/O power consuming circuit is an electric fuse circuit which uses the I/O power source cell as a power source for programming.

3. The system LSI of claim 1 , wherein the first I/O power consuming circuit is an electric fuse circuit which uses the I/O power source cell as a power source for programming.

Assignments (4)
CHANGE OF NAME Recorded Mar 21, 2025
From: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 070747/0799 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
CHANGE OF NAME Recorded Nov 24, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2007
From: AGATA, YASUHIRO; KAWASAKI, TOSHIAKI; SHIRAHAMA, MASANORI; NISHIHARA, RYUJI; SUMI, SHINICHI; YAMAMOTO, YASUE; KIKUKAWA, HIROHITO
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 019048/0956 →