Stacked imager package
View Patent ↗An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
1. A chip package, comprising:
a first chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by through via conductors extending through said first chip from said backside metallurgy to said pads; and
a second chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said first chip by an array of interchip solder bumps.
2. A chip package, comprising:
an imaging chip having backside metallurgy and pads on an active surface thereof positioned around the peripheral region of said active surface, said backside metallurgy connected to said pads by conductors extending from said backside metallurgy to said pads; and
a logic chip having metallurgy on an active surface thereof connected to the said backside metallurgy of said imaging chip by an array of interchip solder bumps.
3. The chip package as set forth in claim 2 wherein the said active surface of said imaging chip includes thereon an array of light sensitive pixels located within the position of said pads around said peripheral region with said pixels arranged to generate voltage as a function of light.
4. The chip package as set forth in claim 3 wherein the said imaging chip is mounted across an aperture in the wall of a carrier package so as to expose said array of light sensitive pixels to light through said aperture.
5. The chip package as set forth in claim 4 wherein said imaging chip and said logic chip are electrically connected to said carrier package by wire bonding.
6. The chip package as set forth in claim 5 wherein said conductors are around-the-edge conductors extending conformally around the edge of said imaging chip to said pads.
7. The chip package as set forth in claim 5 wherein said conductors are through via conductors extending through said imaging chip to said pads.
8. The chip package as set forth in claim 3 wherein the backside of said logic chip is mounted on a carrier package.
9. The chip package as set forth in claim 8 wherein said logic chip is electrically connected to said carrier package by wire bonded at one end to pads on said logic chip and the other end to pads on said carrier package.
10. The chip package as set forth in claim 8 wherein said logic chip is electrically connected to said carrier package by an array of solder bumps with some of said solder bumps of said array of solder bumps connected by through vias to selected ones of said interchip solder bumps.
11. The chip package as set forth in claim 3 wherein the planar area of said logic chip is smaller than the planar area of said imaging chip.