Field effect transistor comprising compound semiconductor
View Patent ↗A field effect transistor having a double recess structure, which minimizes an influence exerted on a channel region depending upon the surface state of an outer recess section. In the field effect transistor having such a double recess structure, an ohmic contact layer at the surface of the outer recess section is made to have a thickness so as to be in a to completely depleted state.
1. A field effect transistor comprising:
a buffer layer;
a channel layer over the buffer layer;
a spacer layer over the channel layer;
a carrier supply layer over the spacer;
a Schottky contact layer over the carrier supply layer;
first and second lower ohmic contact layers over the Schottky contact layer;
a gate electrode disposed between the first and second lower ohmic contact layers;
a first upper ohmic contact layer directly on the first lower ohmic contact layer; and
a second upper ohmic contact layer directly on the second lower ohmic contact layer,
wherein the first and second upper ohmic contact layers are disposed away from the gate electrode and respectively expose top surfaces of the first and second lower ohmic contact layers,
wherein portions of the first and second lower ohmic contact layers exposed by the first and second upper ohmic contact layers are completely depleted, and
wherein each of the first and second lower ohmic contact layers is a material different from that of each of the first and second upper ohmic contact layers.
2. The field effect transistor according to claim 1 , wherein the first and second lower ohmic contact layers are silicon doped InGaAs layers having a dopant concentration of 3×10 18 cm −3 and a thickness of 3 nm.
3. A method of manufacturing a field effect transistor, comprising:
sequentially depositing a buffer layer, a channel layer, a spacer layer, a carrier supply layer, a Schottky contact layer, a lower ohmic contact layer and an upper ohmic contact layer over a semiconductor substrate, the lower ohmic contact layer is completely depleted and the upper ohmic contact layer is directly on the lower ohmic contact layer;
removing part of the upper ohmic contact layer to expose the lower ohmic contact layer, thereby forming an outer recess section;
removing part of the lower ohmic contact layer lying in the outer recess section to expose the Schottky contact layer, thereby forming an inner recess section; and
forming a gate electrode over the Schottky contact layer in the inner recess section,
wherein a material different from that of the upper ohmic contact layer is provided for the lower ohmic contact layer.
4. The method according to claim 3 , further comprising providing the lower ohmic contact layer as a silicon doped InGaAs layer having a dopant concentration of 3×10 18 cm −3 and a thickness of 3 nm.