Parameterizable clip instruction and method of performing a clip operation using the same
A parameterizable clip instruction for SIMD microprocessor architecture and method of performing a clip operating the same. A single instruction is provided with three input operands: a destination address, a source address and a controlling parameter. The controlling parameter includes a range type and a range specifier. The range type is a multi-bit integer in the operand that is used to index a table of range types. The range specifier plugs into the range type to define a range. The data input at the source address is clipped according to the controlling parameters. The instruction is particularly suited to video encoding/decoding applications where interpolations or other calculations, lies outside the maximum value and that final result will have to be clipped to saturation value, for example, the maximum pixel value. Signed and unsigned clipping ranges may be used that are not only powers of two.
1 . A method of causing a microprocessor to perform a clip operation comprising:
providing an assembly instruction to the microprocessor, the instruction comprising an input address, an output address and a controlling parameter;
decoding the instruction with logic in the microprocessor;
retrieving a data input from the input address;
determining a specific clip operation based on the controlling parameter;
performing the clip operation on the data input; and
writing the result to output address.
2 . The method according to claim 1 , wherein determining a clip operation based on the controlling parameter comprises decoding the controlling parameter into a range type and a range specifier.
3 . The method according to claim 2 , wherein the range type is a type selected from the group consisting of a [0, 2 N −1], [−N, N], [− 2 N , 2 N −1] and [0, N], where N is the range specifier.
4 . The method according to claim 2 , wherein decoding the controlling parameter into a range type comprises performing a table look up of a X-bit number in the controlling parameter where 2 X is the number of range types.
5 . The method according to claim 2 , wherein performing the clip operation comprises clipping the input value according to the range type and range specifier.
6 . The method according to claim 1 , wherein in the input address and output addresses comprise vector registers.
7 . A method of performing a clip operation with a single parameterizable assembly language-based clip instruction executing on a microprocessor comprising:
specifying a source address of a data input, a destination address of a clipped output and a controlling parameter in a single instruction;
obtaining the data input at the source address;
performing the clip operation on the data input in accordance with the controlling parameter; and
storing the result at the destination address.
8 . The method according to claim 7 , wherein specifying a controlling parameter comprises specifying a Y bit number including a range type and a range specifier, where Y is an integer power of 2.
9 . The method according to claim 8 , wherein the range type is a is a type selected from the group consisting of a [0, 2 N −1], [−N, N], [−2 N , 2 N −1] and [0, N], where N is the range specifier.
10 . The method according to claim 9 , wherein the range specifier is a positive integer.
11 . The method according to claim 8 , wherein performing the clip operation in accordance with the controlling parameter comprises clipping the data input based on the instruction's range specifier and range type.
12 . The method according to claim 7 , wherein the source address and destination address comprise vector registers and performing the clip operation comprises performing the clip operation in accordance with the controlling parameter on each slice of the source address vector registers and storing the results at a corresponding slice of the destination address vector register.
13 . A parameterizable assembly language program instruction for performing a clip operation in an video processing application comprising:
an instruction name for a particular microprocessor instruction;
a first instruction input operand comprising a destination register address to write an instruction result;
a second instruction input operand comprising a source register address containing a value to be clipped; and
a third instruction input operand comprising a controlling parameter.
14 . The instruction according to claim 13 , wherein the controlling parameter comprises a Z-bit number wherein Z is an integer power of 2.
15 . The instruction according to claim 13 , wherein the controlling parameter includes a range type and a range specifier.
16 . The instruction according to claim 15 , wherein the range type is a type selected from the group consisting of a [0, 2 N −1], [−N, N], [−2 N , 2 N −1] and [0, N], where N is the range specifier.
17 . The instruction according to claim 16 , wherein N is a positive integer.
18 . The instruction according to claim 13 , wherein the destination register address and the source register address are vector register addresses.