Systems and methods for synchronizing multiple processing engines of a microprocessor
Systems and methods for synchronizing multiple processing engines of a microprocessor. In a microprocessor engine employing processor extension logic, DMA engines are used to permit the processor extension logic to move data into and out of local memory independent of the main instruction pipeline. Synchronization between the extended instruction pipeline and DMA engines is performed to maximize simultaneous operation of these elements. The DMA engines includes a data-in and data-out engine each adapted to buffer at least one instruction in a queue. If, for each DMA engine, the queue is full and a new instruction is trying to enter the buffer, the DMA engine will cause the extended pipeline to pause execution until the current DMA operation is complete. This prevents data overwrites while maximizing simultaneous operation.
1 . A method for synchronizing multiple processing engines of a microprocessor comprising:
coupling an extended instruction pipeline to a main instruction pipeline;
coupling direct memory access (DMA) engines to the extended instruction pipeline;
buffering at least one instruction in the DMA engine, using a queue, without stopping the extended instruction pipeline; and
blocking the extended instruction pipeline from further execution when a DMA engine instruction queue is full and a new DMA instruction arrives at the queue, until a current DMA operation is complete.
2 . The method according to claim 1 , wherein coupling DMA engines to the extended instruction pipeline comprises coupling a DMA engine having a data-in channel for moving data into a local memory and a DMA engine having a data-out channel for moving data out of a local memory of the extended instruction pipeline.
3 . The method according to claim 2 , wherein blocking the extended instruction pipeline from issuing subsequent instructions until a DMA operation is complete when any DMA engine instruction queue is full, and a new DMA instruction is being issued to it.
4 . The method according to claim 1 , further comprising restarting execution of the extended instruction pipeline when the DMA operation is complete and the new DMA operation that was trying the enter the buffer successfully leaves the instruction pipeline and enters the instruction queue.
5 . A multi-processing engine architecture for a microprocessor comprising:
a main instruction pipeline;
an extended instruction pipeline coupled to the main instruction pipeline via an instruction queue; and
direct memory access (DMA) engines coupled to the extended instruction pipeline, the DMA access engines comprising a data-in engine and a data-out engine, wherein each of the data-in and data-out engines comprise an instruction queue adapted to buffer at least one instruction.
6 . The architecture according to claim 5 , wherein the DMA access engines are adapted to prevent the extended instruction pipeline from executing additional instructions when the DMA instruction queue is full and a new DMA instruction is blocked from entering the buffer, until a current DMA operation is completed allowing the blocked DMA operation to enter the buffer from the instruction pipeline.
7 . The architecture according to claim 6 , wherein the DMA access engine is adapted to cause the extended instruction pipeline to resume execution once the DMA instruction trying to enter the DMA buffer that was blocked previously enters the DMA instruction buffer when the current DMA operation is completed.
8 . In a microprocessor having a main instruction pipeline and processor extension logic comprising an extended instruction pipeline that is coupled to the main instruction pipeline via an instruction queue, wherein the extended instruction pipeline is adapted to be selectively decoupled from the main instruction pipeline to perform autonomous operation, and where the extended instruction pipeline is further coupled to DMA engines for moving data into and moving data out of a local memory, a method for maximizing simultaneous operation of the extended instruction pipeline and the DMA engines comprising:
executing an instruction from the extended instruction pipeline requiring the DMA engine;
buffering the instruction if sufficient buffer space is available in the DMA engine instruction queue; and
preventing the extended instruction pipeline from further execution if insufficient queue space is available until a current DMA operation is complete, freeing up a space in the queue to accept a blocked DMA instruction on the instruction pipeline, thereafter resuming execution of the extended processor pipeline.