IP Library Granted Patent US 7,729,445
Granted Patent B2
US 7,729,445 · App. 11/528,812 · Granted Jun 1, 2010

Digital outphasing transmitter architecture

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,729,445
App. No.
11/528,812
Granted
Jun 1, 2010
Kind
B2
Abstract

Architectures including digital outphasing transmitters. Digital signal generation circuitry generates at least two base-band sinusoid signals. Bandpass modulation circuitry is coupled to receive the base-band sinusoid signals and generates at least two modulated digital signals. Power amplifiers are coupled to receive the modulated digital signals to amplify the modulated digital signals. The amplified modulated signals are combined and transmitted.

Claims (29)

1. A method comprising:

two digital signal processor (DSP) generators that each generate two streams of constant envelope signals;

performing digital amplitude modulation and digital phase modulation with a pair of sigma-delta modulators coupled with the two DSP generators on a plurality of base-band sinusoid signals to generate corresponding digital modulated signals;

driving a plurality of non-linear power amplifiers with the digital modulated signals, wherein the power amplifiers are configured as power oscillators that are injection locked to the digital modulated signals after upconversion;

providing digital compensation for a total gain/phase unbalance of each signal path; and

combining output signals from the power amplifiers with a passive power combiner.

2. The method of claim 1 further comprising:

adjusting the phase of the modulated signals via digital control; and

providing the phase-adjusted, modulated signals to one or more semi-digital DAC/filters.

3. The method of claim 1 wherein the plurality of base-band sinusoid signals comprises two base-band sinusoid signals and the plurality of power amplifiers comprises two power amplifiers.

4. The method of claim 1 wherein the plurality of power amplifiers comprises N power amplifiers where N is an even number greater than 2.

5. The method of claim 1 further comprising transmitting the combined output signal.

6. The method of claim 1 wherein the modulation is performed by a digital delta-sigma modulator.

7. The method of claim 1 , wherein the plurality of base-band sinusoid signals comprise two anti-phase signals, the method further comprising:

determining an error in response to the combined output signal from the power amplifiers;

using the error to modify generation of subsequent base-band sinusoid signals.

8. An apparatus comprising:

digital signal generation circuitry to generate at least two base-band sinusoid signals derived from a pair of phasors having the same amplitude and centered at the same frequency with varying phases;

bandpass modulation circuitry coupled to receive the base-band sinusoid signals and to generate at least two modulated digital signals;

at least two power amplifiers coupled to receive the at least two modulated digital signals to amplify the modulated digital signals, wherein the power amplifiers are configured as power oscillators that are injection locked to the digital modulated signals after upconversion; and

a passive power combiner coupled with the at least two power amplifiers to combine amplified digital signals for transmission.

9. The apparatus of claim 8 further comprising one or more semi-digital DAC/filters coupled to receive the phase of the modulated signals.

10. The apparatus of claim 8 wherein the modulation is performed by a digital delta-sigma modulator.

11. The apparatus of claim 8 further comprising one or more antenna coupled with the circuitry to combine the digital signals to transmit the combined amplified signal.

12. The apparatus of claim 8 , wherein the plurality of base-band sinusoid signals comprise two anti-phase signals, the apparatus further comprising:

an error determination circuit coupled power amplifiers, the error determination circuit to determine an error in response to the combined output signal from the power amplifiers; and

feedback circuitry coupled with the error determination circuit to utilize the error to modify generation of subsequent base-band sinusoid signals.

13. The apparatus of claim 8 wherein the plurality of base-band sinusoid signals comprises two base-band sinusoid signals and the plurality of power amplifiers comprises two power amplifiers.

14. The apparatus of claim 8 wherein the plurality of power amplifiers comprises N power amplifiers where N is an even number greater than 2.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2018
From: SKY ROYAL TRADING LIMITED
To: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD
Reel/Frame 044750/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2018
From: INTEL CORPORATION
To: SKY ROYAL TRADING LIMITED
Reel/Frame 045171/0323 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2008
From: RAVI, ASHOKE; ELMALA, MOSTAFA; NICHOLLS, RICHARD; PALASKAS, YORGOS; SOUMYANATH, KRISHNAMURTHY; SOMASEKHAR, DINESH
To: INTEL CORPORATION
Reel/Frame 020738/0830 →
Continuity (1)
Related Publication 20080075194A1 · Mar 27, 2008