Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.
1. A method for manufacturing a semiconductor device comprising:
forming an etch stop layer in a top surface of a wafer;
forming a thin junction receiving layer atop said etch stop layer;
forming a junction pattern in said thin junction receiving layer;
forming spaced contacts atop said junction pattern;
attaching a wafer carrier mount to a top surface of said junction pattern, wherein said wafer carrier mount functions to provide a mechanical wafer strength to said wafer;
removing a bulk of said wafer from a bottom of said wafer to said etch stop layer;
metallizing an exposed bottom surface of said junction pattern with a conductive layer; and
removing said wafer carrier mount.
2. The method of claim 1 , wherein said thin junction receiving layer comprises a layer of epitaxially grown silicon.
3. The method of claim 1 , wherein said wafer comprises a monocrystalline silicon.
4. The method of claim 1 , wherein said thin junction receiving layer comprises a thin N + type drain region.
5. The method of claim 4 , wherein said thin junction receiving layer comprises an N − type epitaxially grown layer atop said thin N + type drain region.
6. The method of claim 1 , wherein said removing said bulk of said wafer includes grinding and etching to said etch stop layer.
7. The method of claim 1 further comprising:
forming a via through said thin junction receiving layer;
filling said via with a conductive material to connect at least one of said spaced contacts to said conductive layer on said exposed bottom surface of said wafer.
8. The method of claim 1 , wherein said conductive layer comprises copper.
9. The method of claim 8 , wherein said copper has a thickness greater than about 10 micrometers.
10. The method of claim 1 wherein said wafer has a thickness greater than about 300 micrometers.
11. The method of claim 1 wherein said thin junction receiving layer has a thickness less than about 10 micrometers.
12. The method of claim 1 wherein said spaced contacts are substantially coplanar.
13. The method of claim 1 wherein said wafer carrier provides sufficient strength to said thin junction receiving layer to allow handling without damage.
14. The method of claim 1 wherein said metallization of said exposed bottom surface comprises metallizing with said conductive layer of sufficient thickness and strength to allow handling without damage.
15. A method for manufacturing a semiconductor device comprising:
forming an etch stop layer in a top surface of a silicon wafer;
forming a thin junction receiving layer of silicon atop said etch stop layer;
forming a junction pattern in said thin junction receiving layer;
forming spaced contacts atop said junction pattern;
attaching a wafer carrier mount to a top surface of said junction pattern, wherein said wafer carrier mount functions to provide a mechanical wafer strength to said wafer;
removing a bulk of said wafer from a bottom of said wafer to said etch stop layer;
metallizing an exposed bottom surface of said junction pattern with a conductive layer; and
removing said wafer carrier mount.
16. The method of claim 15 , wherein said thin junction receiving layer of silicon comprises a thin N + type drain region.
17. The method of claim 16 wherein said thin junction receiving layer comprises an N − type epitaxially grown layer atop said thin N + type drain region.
18. The method of claim 15 further comprising:
forming a via through said thin junction receiving layer of silicon;
filling said via with a conductive material to connect at least one of said spaced contacts to said conductive layer on said exposed bottom surface of said wafer.