Electronic device substrate and its fabrication method, and electronic device and its fabrication method
View Patent ↗An electronic device substrate is formed of a thin-plate reinforcing substrate; an external connection wiring layer stacked on the reinforcing substrate, and comprising an electrical insulation provided on the reinforcing substrate, an opening formed in the electrical insulation, a first conductor pattern and a via-hole conductor provided in the opening and formed integrally with each other; and a second conductor pattern formed on the opposite side of the electrical insulation to the reinforcing substrate, and at least partially electrically connected to the via-hole conductor.
1. An electronic device substrate, comprising:
a thin-plate core substrate;
an external connection wiring layer stacked on the core substrate, and comprising an electrical insulation provided on the core substrate, an opening formed in the electrical insulation, a first conductor pattern and a via-hole conductor provided in the opening and formed integrally with each other;
an air layer between the first conductor pattern and the core substrate; and
a second conductor pattern formed on the opposite side of the electrical insulation to the core substrate, and at least partially electrically connected to the via-hole conductor;
wherein the core substrate is releasable from the electrical insulation.
2. The electronic device substrate according to claim 1 , wherein:
The core substrate comprises any of metallic materials comprising acryl, epoxy, polyimide, or adhesive coated thereover, or a combination thereof.
3. The electronic device substrate according to claim 1 , wherein:
the first conductor pattern and the via-hole conductor integral with each other comprise a single layer of an element of gold, silver, copper, nickel, palladium, tin, rhodium, or cobalt, or an alloy thereof, or a stacked layer thereof.
4. The electronic device substrate according to claim 1 , wherein:
the first conductor pattern and the via-hole conductor integral with each other comprise in its constituents at least 5 μm or more copper or its alloy plating, or 3 μm or more nickel or its alloy plating.
5. The electronic device substrate according to claim 1 , wherein:
a height (thickness) of the first conductor pattern and the via-hole conductor integral with each other is smaller than a height (thickness) of the electrical insulation.
6. The electronic device substrate according to claim 1 , wherein:
the electrical insulation comprises solder resist or photo-solder resist.
7. The electronic device substrate, according to claim 1 , wherein an interface between the via-hole conductor and the second conductor pattern is provided at a same level as an upper surface of the electrical insulation.
8. The electronic device substrate, according to claim 1 , wherein an upper surface of the via-hole conductor and an upper surface of the electrical insulation are at a same level.
9. The electronic device substrate, according to claim 1 , wherein the first conductor pattern and the second conductor pattern are made of different materials.
10. The electronic device substrate, according to claim 1 , wherein the first conductor pattern and the second conductor pattern are separate, non-continuous layers.
11. The electronic device substrate, according to claim 1 , wherein the first conductor pattern and the second conductor pattern are formed by separate processing steps.
12. The electronic device substrate, according to claim 1 , wherein the first conductor pattern and the second conductor pattern are different layers.