Selective trace cache invalidation for self-modifying code via memory aging
View Patent ↗Selective trace cache invalidation for self-modifying code via memory aging advantageously retains some of the entries in a trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. Associated with each trace cache entry are translation ages that are determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein processed, the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented. If one of the current ages overflows, then the entire trace cache is flushed.
1. A method comprising:
advancing a current age associated with a memory block in response to a modification of the memory block;
flushing an entire trace cache in response to the advancing resulting in an overflow of the current age; and
associating a sample of the current age with an entry comprised in the trace cache.
2. The method of claim 1 , further comprising detecting at least a processor write to any portion of the memory block as the modification.
3. The method of claim 1 , further comprising detecting at least a device write to any portion of the memory block as the modification.
4. The method of claim 1 , further comprising comparing the sample with the current age in association with speculatively executing at least one micro-operation provided from the entry.
5. The method of claim 4 , further comprising if the comparing determines that the sample and the current age are different, then selectively invalidating the entry.
6. The method of claim 1 , wherein the current age is a first current age, and further comprising resetting the first current age and a second current age in response to the flushing.
7. The method of claim 1 , further comprising in response to the flushing, omitting the advancing until another entry is created in the trace cache.
8. The method of claim 1 , wherein the entry is one of a plurality of entries comprised in the trace cache and further comprising resetting the current age in response to invalidating a last one of the entries having the memory block underlying.
9. The method of claim 1 , further comprising via a processor, accessing a mass storage array in response to the modification.
10. A system comprising:
a trace cache comprising one or more entries enabled to retain micro-operations;
one or more sampled ages associated with each of the entries; and
a control element enabled to:
set the sampled ages in accordance with current ages of memory blocks underlying the entries;
in response to modifications of any portion of the memory blocks, advance the current ages of the modified memory blocks; and
one or more memory block identifiers associated with each of the entries, and wherein the control element is further enabled to set the memory block identifiers to identify the memory blocks,
wherein the control element is further enabled to manage ignore-write properties of the memory blocks, and to omit the advance of a particular one of the modified memory blocks when the ignore-write property of that memory block is set.
11. The system of claim 10 , wherein the control element is further enabled to set all of the ignore-write properties in response to flushing the trace cache.
12. The system of claim 10 , wherein the control element is further enabled to direct selective invalidation of a selected one of the entries.
13. The system of claim 10 , wherein the control element is further enabled to direct flushing the trace cache in response to an overflow of any of the current ages.
14. The system of claim 10 , wherein the trace cache is enabled to provide the micro-operations to one or more processor cores.
15. The system of claim 14 , further comprising the one or more processor cores.