Transmitter power amplifier ramping method
View Patent ↗A method for reducing frequency glitches in a digital transceiver due to power amplifier input impedance variations. According to the method, the power amplifier is switched on after the end of a prior packet reception period and before a new packet transmission begins. Instead of ramping the power amplifier gain, the method ramps the modulation signals. As a consequence, any VCO frequency transients that may result from turning on the power amplifier have an opportunity to decay before the new packet transmission is initiated. This technique effectively isolates the transmitter power amplifier from the frequency synthesizer VCO to facilitate fast switching transceiver operation.
1. A transceiver, comprising:
a receiver;
a transmitter including a power amplifier, and a pair of up-converter mixers;
a frequency synthesizer including a voltage controlled oscillator (VCO);
a controller for isolating the power amplifier and the VCO, comprising:
means for switching on the power amplifier after an end of a prior packet reception period, and
means for ramping modulation signals supplied to the up-converter mixers upon initiation of a new packet transmission.
2. The transceiver as described in claim 1 wherein the modulation signals are in-phase and quadrature-phase modulation signals.
3. The transceiver as described in claim 2 wherein the ramping means monotonically scales a set of digital words representing the in-phase and quadrature-phase signals.
4. The transceiver as described in claim 2 wherein the ramping means includes:
means for generating an analog ramping signal; and
means for applying the analog ramping signal to the in-phase and quadrature-phase baseband signals.
5. The transceiver as described in claim 4 wherein the means for applying is a multiplier.
6. The transceiver as described in claim 1 that is compliant with the IEEE 802.11 standard.
7. A transceiver for use in a wireless local area network (WLAN), comprising:
a radio circuit including a power amplifier, a pair of up-converter mixers, and a frequency synthesizer;
a processor coupled to the radio circuit and including means for generating modulation signals that are supplied to the up-converter mixers; and
a controller for switching on the power amplifier at an end of a prior packet reception period and for ramping the modulation signals supplied to the up-converter mixers upon initiation of a new packet transmission.
8. The transceiver as described in claim 7 wherein the controller monotonically scales a set of digital words representing modulation signals.
9. The transceiver as described in claim 7 wherein the controller includes:
means for generating an analog ramping signal; and
means for applying the analog ramping signal to the modulation signals.
10. A transceiver, comprising:
a receiver;
a transmitter including a power amplifier, and a pair of up-converting mixers;
a frequency synthesizer including a voltage controlled oscillator;
a controller for isolating the power amplifier in advance of packet transmission; and
means for ramping modulation signals supplied to the up-converter mixers upon initiation of a new packet transmission.
11. A transceiver as described in claim 10 , further comprising means for ramping down signals at the end of packet transmission.
12. A transceiver, comprising:
a receiver;
a transmitter having a power amplifier, a first up-converter mixer, and a second up-converter mixer;
a frequency synthesizer having a voltage controlled oscillator (VCO);
a controller operable to isolate the power amplifier from the VCO, the controller including:
a switch operable to switch on the power amplifier after an end of a prior packet reception period, and
a ramping circuit operable to ramp a first modulation signal supplied to the first up-converter mixer and further operable to ramp a second modulation signal supplied to the second up-converter mixer upon initiation of a new packet transmission.
13. The transceiver of claim 12 , further comprising:
a modulation signal generating circuit operable to generate in-phase and quadrature-phase modulation signals.
14. The transceiver of claim 12 wherein the ramping circuit is further operable to monotonically scale a set of digital words representing in-phase and quadrature-phase signals.
15. The transceiver of claim 12 wherein the ramping circuit includes:
a generating circuit operable to form an analog ramping signal; and
a multiplier circuit operable to apply the analog ramping signal to in-phase and quadrature-phase baseband signals.
16. A method of operating a transceiver, comprising:
determining that a packet is to be transmitted;
operating a power amplifier after determining that the packet is to be transmitted;
ramping baseband in-phase and quadrature-phase modulation signals;
supplying the ramped baseband in-phase and quadrature-phase modulation signals to respective up-converter mixers.
17. The method of claim 16 wherein determining the packet is to be transmitted includes determining completion of a packet reception period and operating the power amplifier after determining that the packet is to be transmitted includes switching on the power amplifier after the completion of the packet reception period.
18. The method of claim 17 wherein determining completion of the packet reception period includes identifying a field in a received packet and analyzing the contents of the field.
19. The method of claim 16 wherein ramping baseband in-phase and quadrature-phase modulation signals includes monotonically scaling a set of digital words representing the baseband in-phase and quadrature-phase modulation signals.
20. The method of claim 16 wherein ramping baseband in-phase and quadrature-phase modulation signals includes generating circuit an analog ramping signal and multiplying the in-phase and quadrature-phase baseband signals by the analog ramping signal.