III-nitride semiconductor fabrication
View Patent ↗A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.
1. A process for fabricating a semiconductor device, comprising:
growing a first N-polar III-nitride semiconductor body over a support body;
growing a second N-polar III-nitride semiconductor body over said first N-polar III-nitride semiconductor body;
growing a third N-polar III-nitride semiconductor body over said second N-polar III-nitride semiconductor body;
growing a protective spacer body over said third III-nitride semiconductor body;
removing a portion of said protective spacer body to define an opening therein exposing a portion of said third III-nitride semiconductor body;
growing a fourth N-polar III-nitride semiconductor body at least over said exposed portion;
forming a gate structure over said fourth III-nitride semiconductor body; and
forming power electrodes each electrically coupled to said third III-nitride semiconductor body.
2. The process of claim 1 , wherein said first and said third III-nitride semiconductor bodies are comprised of GaN, and said second and said fourth III-nitride semiconductor bodies are comprised of AlGaN.
3. The process of claim 1 , wherein said support body is comprised of a substrate and a buffer layer disposed on said substrate.
4. The process of claim 3 , wherein said substrate is comprised of silicon.
5. The process of claim 3 , wherein said substrate is comprised of silicon carbide.
6. The process of claim 3 , wherein said substrate is comprised of sapphire.
7. The process of claim 3 , wherein said buffer layer is comprised of a III-nitride body.
8. The process of claim 3 , wherein said buffer layer is comprised of AlN.
9. The process of claim 1 , wherein said support body is comprised of a III-nitride material.
10. The process of claim 1 , wherein said support body is comprised of GaN.
11. The process of claim 1 , wherein said gate structure is comprised of a gate insulation and a gate electrode.
12. The process of claim 1 , wherein said gate structure makes a schottky contact with said fourth III-nitride semiconductor body.
13. The process of claim 1 , wherein said protective spacer body is comprised of at least one of Ge, SiO 2 , Si 3 N 4 , and Al 2 O 3 .
14. A process for fabricating a semiconductor device, comprising:
growing a first N-polar III-nitride semiconductor body over a support body;
growing a second N-polar III-nitride semiconductor body over said first N-polar III-nitride semiconductor body;
growing a third N-polar III-nitride semiconductor body over said second N-polar III-nitride semiconductor body;
growing a protective spacer body over said third N-polar III-nitride semiconductor body;
removing a portion of said protective spacer body to define an opening therein exposing a portion of said third N-polar III-nitride semiconductor body;
forming a gate structure over said third N-polar III-nitride semiconductor body; and
forming power electrodes each electrically coupled to said third N-polar III-nitride semiconductor body after forming said gate structure.
15. The process of claim 14 , further comprising removing a portion of said protective spacer body adjacent said gate structure to expose at least said third III-nitride semiconductor body, forming an insulation body over said gate structure and at least over said exposed portion adjacent said gate structure, removing at least a portion of the remainder of said protective spacer body to expose at least a portion of said third III-nitride semiconductor body; and forming power electrodes over said exposed portions of said third III-nitride semiconductor body.
16. The process of claim 14 , wherein said first and said third III-nitride semiconductor bodies are comprised of GaN, and said second III-nitride semiconductor body is comprised of AlGaN.
17. The process of claim 14 , wherein said support body is comprised of a substrate and a buffer layer disposed on said substrate.
18. The process of claim 17 , wherein said substrate is comprised of at least one of silicon, silicon carbide, or sapphire.
19. The process of claim 17 , wherein said buffer layer is comprised of a III-nitride body.
20. The process of claim 17 , wherein said buffer layer is comprised of AlN.
21. The process of claim 14 , wherein said support body is comprised of a III-nitride material.
22. The process of claim 14 , wherein said support body is comprised of GaN.
23. The process of claim 14 , wherein said gate structure is comprised of a gate insulation and a gate electrode.
24. The process of claim 14 , wherein said gate structure makes a schottky contact with said fourth III-nitride semiconductor body.
25. The process of claim 14 , wherein said protective spacer body is comprised of one of Ge, SiO 2 , Si 3 N 4 and Al 2 O 3 .