Clock synchronization and distribution over an optical Ethernet network
View Patent ↗A novel clock synchronization mechanism for recovering and distributing a centralized clock source synchronously over asynchronous networks such as optical Ethernet. A clock conversion scheme is provided whereby multiple clocks having diverse rates are converted to clock signals all having a common rate. One of the converted clocks is chosen and all downstream clock signals is derived from this clock. A high quality clock source located anywhere on the network is distributed throughout the network thus turning an asynchronous Ethernet network into a synchronous one. Synchronous TDM data streams can then be easily transported over the Ethernet network.
1. A method of distributing a centralized clock source synchronously over an asynchronous optical Ethernet network, said method comprising the steps of:
receiving a plurality of available input asynchronous optical Ethernet signals of various rates, zero or more available input clock signals and zero or more input time division multiplexing (TDM) signals, and recovering clock signals therefrom, each recovered clock signal having a rate associated therewith;
translating the rate of each receive clock signal and any available input clock signals to a common rate to generate a plurality of common rate receive clock signals;
selecting one of said common rate receive clock signals to serve as a primary clock;
generating one or more regenerated Ethernet clock signals and one or more output clock signals from said primary clock signal, wherein a separate Ethernet clock signal at a particular rate is generated for each required Ethernet clock; and
generating one or more transmit optical Ethernet signals utilizing said regenerated Ethernet clock signals, thereby distributing a clock source over said asynchronous optical Ethernet network.
2. The method according to claim 1 , wherein said input Ethernet signal comprises a 100 Mbps Fast Ethernet signal.
3. The method according to claim 1 , wherein said optical Ethernet signal comprises a 1 G optical Ethernet signal.
4. The method according to claim 1 , wherein said optical Ethernet signal comprises a 10 G optical Ethernet signal.
5. The method according to claim 1 , wherein the selection of said primary clock source is based on clock quality measurements.
6. The method according to claim 1 , wherein said input clock signals comprise one or more backplane clock input signals.
7. The method according to claim 1 , wherein said input clock signals comprise one or more Clock Ethernet Synchronization (CES) card clock input signals.
8. The method according to claim 1 , wherein said common rate is 8 kHz.
9. The method according to claim 1 , further comprising the step of selecting a second clock signal from said plurality of common rate receive clock signals to serve as a secondary clock.
10. The method according to claim 1 , further comprising the step of performing jitter attenuation on said one or more generated Ethernet clock signals.
11. The method according to claim 1 , further comprising the step of generating and transmitting synchronization status messages adapted to convey clock quality information from one node to another in said asynchronous optical Ethernet network.
12. The method according to claim 1 , wherein said step of generating one or more regenerated Ethernet clock signals utilizes a digital phase locked loop (PLL) circuit to generate said one or more Ethernet output clocks based on said primary clock.
13. The method according to claim 1 , wherein said step of generating one or more regenerated Ethernet clock signals utilizes an analog phase locked loop (PLL) circuit to generate said one or more Ethernet output clocks based on said primary clock.
14. An apparatus for distributing a centralized clock source synchronously over an asynchronous optical Ethernet network, comprising:
a plurality of clock recovery circuits operative to extract recovered clock signals from a plurality of input asynchronous optical Ethernet signals of various rates, zero or more available input clock signals and zero or more input time division multiplexing (TDM) signals, each recovered clock signal having a clock rate associated therewith;
a clock rate adaptation circuit operative to translate the clock rate of each recovered clock signal to a common rate to generate a plurality of common rate receive clock signals thereby;
selection means for selecting one of said plurality of common rate receive clock signals to serve as a primary clock; and
a clock regeneration circuit operative to generate one or more regenerated Ethernet clock signals from said primary clock signal, wherein a separate Ethernet clock signal at a particular rate is generated for each required Ethernet transmit clock.
15. The apparatus according to claim 14 , wherein said input Ethernet signal comprises a 100 Mbps Fast Ethernet signal.
16. The apparatus according to claim 14 , wherein said input optical Ethernet signal comprises a 1 G optical Ethernet signal.
17. The apparatus according to claim 14 , wherein said input optical Ethernet signal comprises a 10 G optical Ethernet signal.
18. The apparatus according to claim 14 , wherein the selection of said primary clock source is based on clock quality measurements.
19. The apparatus according to claim 14 , wherein said input clock signals comprises one or more backplane clock input signals.
20. The apparatus according to claim 14 , wherein said input clock signals comprises one or more Clock Ethernet Synchronization (CES) card clock input signals.
21. The apparatus according to claim 14 , wherein said common rate is 8 kHz.
22. The apparatus according to claim 14 , wherein said selection means further comprises means for selecting a second clock signal from said plurality of common rate receive clock signals to serve as a secondary clock.
23. The apparatus according to claim 14 , wherein said clock regeneration circuit comprises a jitter attenuation circuit.
24. The apparatus according to claim 14 , wherein said clock regeneration circuit comprises a phase locked loop circuit.
25. The apparatus according to claim 14 , further comprising means for generating and transmitting synchronization status messages adapted to convey clock quality information from one node to another in said asynchronous optical Ethernet network.
26. A method of distributing a centralized clock source synchronously over an asynchronous optical Ethernet network, said method comprising the steps of:
receiving a plurality of ingress data signals from a plurality of optical Ethernet or zero or more time division multiplexing (TDM) signal sources and recovering a clock signal from each ingress data signal and TDM signal, each recovered clock signal having a clock rate associated therewith, wherein at least one of said ingress data signals is derived from a high quality clock;
adapting the rate of each recovered clock signal to a common rate to yield a plurality of common rate clock signals;
selecting a first common rate clock derived from a high quality clock to serve as a primary clock and a second common rate clock to serve as a secondary clock;
generating one or more regenerated Ethernet clock signals from said primary clock signal, wherein a separate Ethernet clock signal at a particular rate is generated for each required Ethernet clock; and
generating one or more transmit optical Ethernet signals utilizing said regenerated Ethernet clock signals, thereby distributing a high quality clock source over said asynchronous optical Ethernet network.
27. The method according to claim 26 , wherein said step of receiving comprises receiving zero or more input clock sources and recovering a clock signal therefrom.
28. A provider edge switch for use in an asynchronous optical Ethernet based network, comprising:
a plurality of line cards incorporating one or more ports for interfacing said provider edge switch to one or more users or other provider switches, each line card comprising:
a plurality of ports, each port coupled to a network communications link;
a packet processing engine coupled to said plurality of ports, said packet processing engine for determining forwarding decision and destination queue for each ingress packet;
a queue manager coupled to said packet processing engine;
a synchronous clock module for distributing a centralized clock source synchronously over an asynchronous optical Ethernet network, said synchronous clock module comprising:
a plurality of clock recovery circuits operative to extract recovered clock signals from a plurality of input asynchronous optical Ethernet signals of various rates, zero or more available input clock signals and zero or more input time division multiplexing (TDM) signals, each recovered clock signal having a clock rate associated therewith;
a clock rate adaptation circuit operative to translate the clock rate of each recovered clock signal to a common rate to generate a plurality of common rate receive clock signals thereby;
selection means for selecting one of said plurality of common rate receive clock signals to serve as a primary clock;
a clock regeneration circuit operative to generate one or more regenerated Ethernet clock signals from said primary clock signal, wherein a separate Ethernet clock signal at a particular rate is generated for each required Ethernet transmit clock; and
switching means coupled to said queue manager and adapted to provide switching fabric functionality to said provider edge switch.
29. A core switch for use in an asynchronous optical Ethernet based network, comprising:
a plurality of line cards incorporating one or more ports for interfacing said network edge switch to one or more users;
a clock synchronization circuit coupled to said plurality of ports for distributing a centralized clock source synchronously over said asynchronous optical Ethernet network, said clock synchronization circuit operative to:
receive a plurality of available input asynchronous optical Ethernet signals of various rates, zero or more available input clock signals and zero or more input time division multiplexing (TDM) signals, and recover clock signals therefrom, each recovered clock signal having a rate associated therewith;
translate the rate of each receive clock signal and any available input clock signals to a common rate to generate a plurality of common rate receive clock signals;
select one of said common rate receive clock signals to serve as a primary clock;
generate one or more regenerated Ethernet clock signals and one or more output clock signals from said primary clock signal, wherein a separate Ethernet clock signal at a particular rate is generated for each required Ethernet clock; and
generate one or more transmit optical Ethernet signals utilizing said regenerated Ethernet clock signals thereby distributing a clock source over said asynchronous optical Ethernet network.