Electronically resettable current protection for die testing
View Patent ↗Electronically reset table test apparatus. The test apparatus includes an electronically operable current breaker connected to a test jig for testing semiconductor die. The electronically operable current breaker is connected through an interface that converts signals to signals appropriate for use on a computer bus to a computer system. The test apparatus can detect faults in the semiconductor die and open the electronically operable current breaker in response to detecting the fault. The electronically operable current breaker can be closed when the fault is removed.
1. A test apparatus for testing a semiconductor die, the test apparatus comprising:
a test jig configured to accommodate the semiconductor die;
a power source connected to the test jig and configured to supply current to the semiconductor die;
a current sensor coupled to the test jig, the current sensor configured to sense current passing through the semiconductor die;
an electronically operable current breaker connected to the test jig, the electronically operable current breaker configured to selectively complete and break a circuit that includes the power source;
a computer configured to receive signals from the current sensor and to selectively cause the electronically operable circuit breaker to break the circuit including the power source in response to receiving signals from the current sensor indicating that a fault has occurred in the semiconductor die, the computer further configured to selectively cause the electronically operable circuit breaker to complete the circuit that includes the power source in response to the fault being removed; and
an interface connectable between the computer, the current sensor and the electronically operable current breaker, wherein the interface allows the computer to connect to the current sensor and the electronically operable current breaker through a port on the computer.
2. The test apparatus of claim 1 , wherein the port on the computer is an RS232 serial port.
3. The test apparatus of claim 1 , wherein the port on the computer is a USB port.
4. The test apparatus of claim 1 , wherein the port on the computer is a parallel port.
5. The test apparatus of claim 1 , wherein the port on the computer is an IEEE 1394 port.
6. The test apparatus of claim 1 , wherein the port on the computer is a wireless connection.
7. The test apparatus of claim 1 , wherein the interface comprises a USB to SPI interface.
8. The test apparatus of claim 1 , wherein the current sensor comprises a current sense resistor.
9. The test apparatus of claim 1 , wherein the current sensor comprises a coil.
10. The test apparatus of claim 1 , wherein the electronically operable current breaker comprises a transistor.
11. The test apparatus of claim 1 , wherein the electronically operable current breaker comprises a silicon controlled relay.
12. The test apparatus of claim 1 , wherein the electronically operable current breaker comprises a mechanical relay.
13. An interface for use in testing semiconductor dies, the interface comprising:
a power source for supplying current to a semiconductor die;
a current sensor coupled to the power source, the current sensor configured to sense current passing through the semiconductor die that is indicative of a fault in the semiconductor die;
an electronically operable current breaker coupled to the power source for selectively completing or breaking a circuit between the semiconductor die and the power source;
circuitry coupled to the current sensor the circuitry coupled to the current sensor configured to convert signals from the current sensor to a form that is readable by a computer bus; and
circuitry coupled to the electronically operable current breaker, the circuitry coupled to the electronically operable current breaker configured to receive signals from the computer bus and in response generate signals to selectively control the electronically operable current breaker to open or close a circuit including the power source and the semiconductor die, wherein the circuitry opens the electronically operable current breaker when the fault is indicated by the sensed current passing through the semiconductor die.
14. The interface of claim 13 , wherein the computer bus is a SPI bus.
15. The interface of claim 13 , wherein the electronically operable current breaker comprises a current sensing resistor.
16. The interface of claim 13 , wherein the electronically operable current breaker comprises a coil.
17. The interface of claim 13 , wherein the electronically operable current breaker comprises a transistor.
18. The interface of claim 13 , wherein the electronically operable current breaker comprises a silicon controlled relay.
19. The interface of claim 13 , wherein the electronically operable current breaker comprises a mechanical relay.
20. An interface for use in testing semiconductor dies, the interface comprising:
means for supplying current to a semiconductor die;
means for sensing current passing through the semiconductor die that is indicative of a short circuit condition in the semiconductor die;
means for selectively completing or breaking a circuit between the semiconductor die and the power source; means for converting signals from the current sensor to a form that is readable by a computer bus; and
means for receiving signals from the computer bus and in response generating signals to selectively control the electronically operable current breaker to open or close a circuit including the power source and the semiconductor die, wherein the means for receiving closes or opens the circuit when the current indicates a short circuit condition in the semiconductor die.