Method for performing post-synthesis circuit optimization
View Patent ↗Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by using interior point optimization methods. The first method treats gate delays as uncertain quantities and obtains the optimal sizes for gates in a circuit under a probabilistically specified circuit timing target. The second method optimizes total circuit power by using a combination of dual threshold voltage assignment and gate sizing. Both circuit power and timing are treated probabilistically.
1. A computer-implemented method for performing post-synthesis circuit optimization, the method comprising:
receiving, by a computing system, a gate-level description of a circuit to be optimized, wherein the gate-level description includes a plurality of gates;
generating, by the computing system, statistical gate delay models using gate characterizations for each of the plurality of gates and process variability data from a semiconductor manufacturing process characterization, the process variability data including one or more process variability parameters;
formulating, by the computing system, a robust linear program using the statistical gate delay models;
transforming, by the computing system, the robust linear program into a second order conic program; and
solving, by the computing system, the second order conic program to select a gate size for each of the plurality of gates.
2. The method of claim 1 , wherein said generating further comprises:
expressing a nominal delay in terms of a set of linear equations that best approximate a delay of a gate in the absence of process variations; and
modeling an impact of the process variations on gate delay by performing a sensitivity analysis to quantify an effect of each of the one or more process parameters on the delay of a gate.
3. The method of claim 1 , wherein said formulating further includes expressing a deterministic sizing problem as:
min
∑
i
s
i
s
.
t
.
T
max
≤
T
T
max
=
max
(
AT
0
)
Vo
∈
PO
where s i is the size of gate i, T is the specified timing target, T max is the delay of the critical path through the circuit, and AT o is the required arrival time at primary output o.
4. The method of claim 1 , wherein said transforming further includes expressing a computationally efficient program for sizing as:
min
∑
j
s
j
AT
o
≤
T
,
for
Vo
∈
PO
AT
k
≥
AT
j
+
d
_
j
+
ϕ
-
1
(
α
)
σ
d
j
where AT i is the arrival time at node i and T is the required arrival time at primary output o.
5. The computer-implemented method of claim 1 , wherein the computing system comprises at least one of a central processing unit, a main memory, and a storage unit.
6. An article of manufacture, comprising
a computer-readable storage medium; and
a plurality of programming instructions, stored on the computer-readable storage medium, and executable by a computing device to:
generate statistical gate delay models based at least on electrical characterization information from gate characterizations for each of a plurality of gates from a gate-level description and process variability data from a semiconductor manufacturing process characterization, wherein the process variability data includes one or more process variability parameters;
formulate a robust linear program for gate sizing by using the statistical gate delay models;
transform the robust linear program into a second order conic program; and
solve the second order conic program to select a gate size for each of the plurality of gates.
7. The article of manufacture of claim 6 , wherein the plurality of programming instructions are further executable by the computing device to:
express a nominal delay in terms of a set of linear equations that approximate a delay of a gate in the absence of process variations; and
model an impact of the process variations on gate delay by performing a sensitivity analysis to quantify an effect of each of the one or more process parameters on the delay of a gate.
8. The article of manufacture of claim 6 , wherein the plurality of programming instructions are further executable by the computing device to express a deterministic sizing problem as:
min
∑
i
s
i
s
.
t
.
T
max
≤
T
T
max
=
max
(
AT
0
)
Vo
∈
PO
where s i is the size of gate i, T is the specified timing target, T max is the delay of the critical path through the circuit, and AT o is the required arrival time at primary output o.
9. The article of manufacture of claim 6 , wherein the plurality of programming instructions are further executable by the computing device to express a computationally efficient program for sizing as:
min
∑
j
s
j
AT
o
≤
T
,
for
Vo
∈
PO
AT
k
≥
AT
j
+
d
_
j
+
ϕ
-
1
(
∝
)
σ
d
j
where AT i is the arrival time at node i and T is the required arrival time at primary output o.