Thin-film transistor with controllable etching profile

1. A thin-film transistor comprising:

a gate layer, a gate insulating layer, a semiconductor layer, a drain layer, and a passivation layer that are formed one of on an insulating substrate and over said insulating substrate; and

a conductive layer formed on the passivation layer, the conductive layer being connected to one of the gate layer and the drain layer by way of a contact hole penetrating at least the passivation layer,

wherein the passivation layer has a multiple-layer structure comprising at least a first sublayer and a second sublayer stacked, the first sublayer having an etch rate lower than an etch rate of the second sublayer,

wherein the first sublayer is disposed closer to the insulating substrate than the second sublayer,

wherein the second sublayer has a thickness equal to or less than a thickness of the conductive layer,

wherein the passivation layer comprises silicon nitride (SiN), and

wherein a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the second sublayer of the passivation layer comprising SiN is equal to or greater than 2.3 times as much as a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the first sublayer.

2. A thin-film transistor, comprising:

a gate layer, a gate insulating layer, a semiconductor layer, a drain layer, and a passivation layer that are formed one of on an insulating substrate and over said insulating substrate; and

a conductive layer formed on the passivation layer, the conductive layer being connected to one of the gate layer and the drain layer by way of a contact hole penetrating at least the passivation layer,

wherein the passivation layer has a multiple-layer structure comprising at least a first sublayer and a second sublayer stacked, the first sublayer having an etch rate lower than an etch rate of the second sublayer,

wherein the first sublayer is disposed nearer to the insulating substrate than the second sublayer,

wherein the second sublayer has a thickness equal to or less than a thickness of the conductive layer, and

wherein a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the second sublayer of the passivation layer is equal to or greater than 2.3 times as much as a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the first sublayer.

3. A thin-film transistor, comprising:

a gate layer, a gate insulating layer, a semiconductor layer, a drain layer, and a passivation layer that are formed one of on an insulating substrate and over said insulating substrate; and

a conductive layer formed on the passivation layer, the conductive layer being connected to one of the gate layer and the drain layer by way of a contact hole penetrating at least the passivation layer,

wherein the passivation layer has a multiple-layer structure comprising at least a first sublayer, a second sublayer, and a third sublayer stacked, the first sublayer having an etch rate that is lower than an etch rate of the second sublayer, the third sublayer having an etch rate that is greater than said etch rate of said second sublayer and said etch rate of said first sublayer,

wherein the first sublayer is disposed nearer to the insulating substrate than the second sublayer, and

wherein said second sublayer and said third sublayer have thicknesses less than or equal to a thickness of said conductive layer.

4. The thin-film transistor according to claim 3 , wherein said conductive layer comprises a pixel electrode layer.

5. The thin-film transistor according to claim 3 , wherein said passivation layer comprises silicon nitride (SiN).

6. The thin-film transistor according to claim 1 , wherein an entirety of said second sublayer is disposed on a surface of said first sublayer.

7. The thin-film transistor according to claim 3 , wherein said gate layer is formed on an insulating plate, and

wherein said insulating plate is formed nearer to said first sublayer than to said second sublayer.

8. The thin-film transistor according to claim 3 , wherein said second sublayer is formed at an upper portion of said passivation layer and said first sublayer is formed at a lower portion of said passivation layer.

9. The thin-film transistor according claim 3 , wherein said etch rate of said second sublayer is equal to or greater than 1.1 times said etch rate of said first sublayer.

10. The thin-film transistor according claim 3 , wherein a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the second sublayer of the passivation layer is equal to or greater than 2.3 times as much as a ratio of an N atom count bonded to an H atom to a Si atom count bonded to the H atom (N—H/Si—H) of the first sublayer.

11. The thin-film transistor according to claim 3 , wherein said third sublayer is formed at an upper portion of said passivation layer,

wherein said second sublayer is formed at a middle portion of said passivation layer, and

wherein said first sublayer is formed at a bottom portion of said passivation layer.