Liquid crystal display and method for manufacturing the same having particular pad unit
View Patent ↗Disclosed are a liquid crystal display (LCD) and a method for manufacturing the same, in which connection stability is improved when connecting a COG, A COF, or an FPC to a driving circuit. A substrate of the LCD has a display region and a non-display region at a peripheral area thereof. Terminals are provided to electrically connect an external circuit and a circuit of the display region and the non-display region. A flat protective layer is formed on the terminals. A plurality of pads are respectively formed of a first contact region and a flat second contact region, and each of the pads contacts a corresponding terminal, which is formed through a pad contact hold formed on the protective layer, at the first contact region, and each of the pads is electrically connected through an anisotropic conductive resin to a terminal of the external circuit by a pressing process at the flat second contact region.
1. An array substrate comprising:
a substrate including a display region and a non-display region;
a plurality of pixels arranged in the display region;
a pad unit, arranged in the non-display region, for applying a signal to the pixels; and
at least one driving IC having a bump at a terminal of the driving IC, the terminal of the driving IC being electrically connected to the pad unit by the bump,
wherein the pad unit:
a first contact region having a contact hole;
a second contact region adjacent to the first contact region;
a first metal layer arranged over the first and second contact regions;
an insulating layer on the first metal layer, the insulating layer having a plurality of contact holes; and
a second metal layer arranged over the insulating layer and electrically connected to the first metal layer through the contact holes, and
the bump contacts the second metal layer in the second contact region.
2. The array substrate of claim 1 , wherein the terminal of the driving IC further includes an output terminal and an input terminal.
3. The array substrate of claim 1 , wherein the bump is aligned with the second contact region, and a plurality of conductive balls are disposed between the bump and the second metal layer.
4. The array substrate of claim 3 , wherein the conductive balls are compressed between the bump and the second metal layer, for electrically connecting the bump to the second metal layer.
5. The array substrate of claim 1 , further comprising a first peripheral region and a second peripheral region.
6. The array substrate of claim 5 , wherein the pad unit further includes a plurality of data pads formed at the first peripheral region, and a plurality of gate pads formed at the second peripheral region.
7. The array substrate of claim 6 wherein the driving IC further includes a data driving JIG bonded to the data pads at the first peripheral region, and a gate driving IC bonded to the gate pads at the second peripheral region.
8. The array substrate of claim 7 , wherein the data pads are aligned in a zigzag fashion of two rows.
9. The array substrate of claim 8 , wherein the bump of the data driving ICs are aligned in a zigzag fashion of two rows.