Variable modulation with LDPC (low density parity check) coding
View Patent ↗Variable modulation with LDPC (Low Density Parity Check) coding provides for generation of LDPC coded symbols having different respective code rates and/or modulations. In addition, appropriate LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, and/or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.
1. An apparatus that is operable to generate an LDPC (Low Density Parity Check) coded signal, the apparatus comprising:
an LDPC encoder that is operable to encode at least one information bit thereby generating an LDPC codeword;
a serial to parallel mapping block that is operable to partition the LDPC codeword into a first plurality of symbols and a second plurality of symbols;
a first mapper that is operable to map at least one symbol within the first plurality symbols to a first constellation whose constellation points have a corresponding first mapping; and
a second mapper that is operable to map at least one symbol within the second plurality symbols to a second constellation whose constellation points have a corresponding second mapping.
2. The apparatus of claim 1 , wherein:
the at least one symbol within the first plurality symbols is a first symbol within the first plurality symbols; and
the first mapper is operable to map a second symbol within the first plurality symbols to a third constellation having a corresponding third mapping.
3. The apparatus of claim 1 , wherein:
the LDPC codeword includes a first plurality of bits followed by a second plurality of bits;
the first plurality of symbols is formed from the first number of bits of the LDPC codeword; and
the second plurality of symbols is formed from the second number of bits of the LDPC codeword.
4. The apparatus of claim 1 , wherein:
the at least one symbol within the first plurality symbols is a first symbol within the first plurality symbols;
the at least one symbol within the second plurality symbols is a first symbol within the second plurality symbols;
during a first time:
the first mapper is operable to map the first symbol within the first plurality symbols to the first constellation whose constellation points have the corresponding first mapping; and
the second mapper is operable to map the first symbol within the second plurality symbols to the second constellation whose constellation points have the corresponding second mapping; and
during a second time:
the first mapper is operable to map a second symbol within the second plurality symbols to the first constellation whose constellation points have the corresponding first mapping; and
the second mapper is operable to map a second symbol within the first plurality symbols to the second constellation whose constellation points have the corresponding second mapping.
5. The apparatus of claim 1 , wherein:
the serial to parallel mapping block is operable to partition the LDPC codeword into a first LDPC codeword portion and a second LDPC codeword portion; and
a symbol within the first plurality of symbols is formed using a first bit from the first LDPC codeword portion and a second bit from the second LDPC codeword portion.
6. The apparatus of claim 1 , wherein:
the serial to parallel mapping block is operable to partition the LDPC codeword into a first LDPC codeword portion, a second LDPC codeword portion, and a third LDPC codeword portion; and
a symbol within the second plurality of symbols is formed using a first bit from the first LDPC codeword portion, a second bit from the second LDPC codeword portion, and a third bit from the third LDPC codeword portion.
7. The apparatus of claim 1 , wherein:
the serial to parallel mapping block is operable to divide the LDPC codeword into a plurality of paths;
a first bit is selected from a first path of the plurality of paths;
a second bit is selected from a second path of the plurality of paths; and
the first bit and the second bit form a symbol of the LDPC coded signal.
8. The apparatus of claim 1 , wherein:
the at least one information bit is a first information bit;
the LDPC encoder is a variable code rate encoder;
the LDPC encoder is operable to encode the first information bit according to a first code rate; and
the LDPC encoder is operable to encode a second information bit according to a second code rate.
9. The apparatus of claim 1 , wherein:
the LDPC codeword includes a plurality of encoded bits;
a plurality of bits is selected from the plurality of encoded bits;
an order of the selected plurality of bits is re-arranged; and
the selected plurality of bits, after being re-arranged, forms a symbol within the first plurality of symbols.
10. The apparatus of claim 1 , wherein:
at least one bit from the at least one symbol of the first plurality if symbols is punctured.
11. The apparatus of claim 1 , wherein:
the apparatus is a communication device that is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.
12. An apparatus that is operable to generate an LDPC (Low Density Parity Check) coded signal, the apparatus comprising:
an LDPC encoder that is operable to encode at least one information bit thereby generating an LDPC codeword;
a serial to parallel mapping block that is operable to:
partition the LDPC codeword into a first LDPC codeword portion and a second LDPC codeword portion;
form a first symbol using a first bit of the first LDPC codeword portion and a first bit of second LDPC codeword portion; and
form a second symbol using a second bit of the first LDPC codeword portion and a second bit of the second LDPC codeword portion;
a mapper that is operable to:
map the first symbol to a first constellation; and
map the second symbol to a second constellation.
13. The apparatus of claim 12 , wherein:
the first constellation includes a plurality of constellation points that is mapped according to a first mapping; and
the second constellation includes the plurality of constellation points that is mapped according to a second mapping.
14. The apparatus of claim 12 , wherein:
the at least one information bit is a first information bit;
the LDPC encoder is a variable code rate encoder;
the LDPC encoder is operable to encode the first information bit according to a first code rate; and
the LDPC encoder is operable to encode a second information bit according to a second code rate.
15. The apparatus of claim 12 , wherein:
the first bit of the first LDPC codeword portion and the first bit of second LDPC codeword portion are re-arranged before forming the first symbol there from.
16. The apparatus of claim 12 , wherein:
at least one bit of the first symbol is punctured.
17. The apparatus of claim 12 , wherein:
the apparatus is a communication device that is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.
18. A method for generating an LDPC (Low Density Parity Check) coded signal, the method comprising:
performing LDPC encoding of at least one information bit thereby generating an LDPC codeword;
partitioning the LDPC codeword into a first LDPC codeword portion and a second LDPC codeword portion;
forming a first symbol using a first bit of the first LDPC codeword portion and a first bit of second LDPC codeword portion; and
forming a second symbol using a second bit of the first LDPC codeword portion and a second bit of the second LDPC codeword portion;
mapping the first symbol to a first constellation; and
mapping the second symbol to a second constellation.
19. The method of claim 18 , wherein:
the first constellation includes a plurality of constellation points that is mapped according to a first mapping; and
the second constellation includes the plurality of constellation points that is mapped according to a second mapping.
20. The method of claim 18 , further comprising:
performing the LDPC encoding of the at least one information bit according to a first code rate; and
performing LDPC encoding of a at least one additional information bit according to a second code rate.