Thin film transistor array panel and method of manufacturing the same
View Patent ↗A thin film transistor (TFT) array panel and method of manufacturing the same are provided. The method includes forming a semiconductor layer and an ohmic contact layer over a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O 2 ) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.
1. A method of manufacturing a thin film transistor (TFT) array panel, the method comprising:
forming a semiconductor layer and an ohmic contact layer over a gate line on a substrate;
forming a conductive layer on the ohmic contact layer;
forming a first photosensitive layer pattern on the conductive layer;
etching the conductive layer using the first photosensitive layer pattern as an etching mask, so as to form an etched surface of the conductive layer, the ohmic contact layer and the semiconductor layer having a projection portion protruding from the etched surface and a covered portion covered by the conductive layer;
etching back the projection portion and etching the covered portion from under the conductive layer with a fluorine-containing gas, a chloride-containing gas, and an oxygen (O 2 ) gas using the first photosensitive layer pattern as an etching mask;
removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern; and
etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.
2. The method of claim 1 , further comprising forming a gate insulation layer between the gate line and the semiconductor layer.
3. The method of claim 2 , wherein the thickness of the gate insulation layer that remains after etching the ohmic contact layer and the semiconductor layer with the fluorine-containing gas, the chloride-containing gas, and the oxygen (O 2 ) gas using the first photosensitive layer pattern as the etching mask is no less than 2,000 Å.
4. The method of claim 2 , wherein when the ohmic contact layer and the semiconductor layer are etched with the fluorine-containing gas, the chloride-containing gas, and the oxygen (O 2 ) gas using the first photosensitive layer pattern as the etching mask, the thickness of the etched gate insulation layer is 1,200 Å to 2,500 Å.
5. The method of claim 1 , wherein the flow ratio between the fluorine-containing gas and the oxygen (O 2 ) gas is in the range of about 4:1 to about 1:1.
6. The method of claim 1 , wherein the flow ratio between the fluorine-containing gas and the oxygen (O 2 ) gas is about 2:1.
7. The method of claim 5 , wherein the flow ratio between the fluorine-containing gas and the chloride-containing gas is about 5:1.
8. The method of claim 5 , wherein:
the fluorine-containing gas comprises at least one gas selected from the group consisting of SF 6 and CF 4 ; and
the chloride containing-gas comprises at least one gas selected from the group consisting of HCl, Cl 2 , CCl 4 , BCl 3 , and SiCl 2 H 2 .
9. The method of claim 5 , wherein the ohmic contact layer and the semiconductor layer are etched using the first photosensitive layer pattern as the etching mask under a pressure of about 100 mT to about 500 mT.
10. The method of claim 1 , wherein the flow ratio between the fluorine-containing gas and the oxygen gas changes in the range of about 4:1 to about 1:1 in accordance with time.
11. The method of claim 1 , wherein the conductive layer comprises a first conductive layer containing molybdenum (Mo), a second conductive layer containing aluminum (Al), and a third conductive layer containing molybdenum (Mo).
12. The method of claim 11 , wherein the conductive layer is wet etched.
13. A method of manufacturing a thin film transistor (TFT) array panel, the method comprising:
forming gate lines on a substrate;
forming a gate insulation layer, a semiconductor layer, and an ohmic contact layer on the gate lines;
forming a conductive layer on the ohmic contact layer;
forming a first photosensitive layer pattern on the conductive layer;
etching the conductive layer using the first photosensitive layer pattern as an etching mask;
etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O 2 ) gas using the first photosensitive layer pattern as an etching mask, wherein the flow ratio between the fluorine-containing gas and the oxygen gas is in the range of about 4:1 to about 1:1;
removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern; and
etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.
14. The method of claim 13 , wherein the flow ratio between the fluorine-containing gas and the oxygen gas is about 2:1.
15. The method of claim 13 , wherein:
the fluorine-containing gas comprises at least one gas selected from the group consisting of SF 6 and CF 4 ; and
the chloride-containing gas comprises at least one gas selected from the group consisting of HCl, Cl 2 , CCl 4 , BCl 3 , and SiCl 2 H 2 .
16. The method of claim 13 , wherein the flow ratio between the fluorine-containing gas and the oxygen gas changes in the range of 4:1 to 1:1 in accordance with time.