Use of an internal on-chip inductor for electrostatic discharge protection of circuits which use bond wire inductance as their load
View Patent ↗A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.
1. A method for constructing a circuit comprising:
forming a plurality of circuit components on a semi conductive substrate die, including:
forming at least one active component that operates on an information signal;
forming a tuning node that couples to the at least one active component;
forming a rail;
forming an Electro Static Discharge (ESD) protection inductor that communicatively couples between the tuning node and the rail, the ESD protection inductor providing ESD protection prior to packaging of the semi conductive substrate die; and
forming a chip pad that couples to the tuning node;
packaging the semi conductive substrate die, including:
mounting the semi conductive substrate die into a package;
coupling a bond wire between the chip pad and a package pad, the bond wire serving as a tuning inductor for the circuit.
2. The method of claim 1 , wherein the ESD protection inductor has a substantially lower Quality (Q) than the bond wire.
3. The method of claim 1 :
wherein the rail is a voltage supply rail; and
further comprising coupling the chip pad to a voltage supply.
4. The method of claim 1 :
wherein the rail is a ground rail; and
further comprising coupling the chip pad to a package ground.
5. The circuit of claim 4 , wherein coupling a bond wire between the chip pad and a package pad comprises coupling the bond wire to a down bond rail of the package that couples to a heat slug upon which the semi conductive die is mounted.
6. The method of claim 1 , wherein the at least one active component is operable to receive a voltage signal and to produce a current signal.
7. The method of claim 1 , wherein forming the ESD protection inductor comprises forming a spiral inductor in a plurality of metal layers upon the semi conductive substrate die.
8. The method of claim 1 , wherein the information signal is an RF signal.
9. The method of claim 8 , wherein the circuit is an RF power amplifier.
10. The circuit claim 1 , wherein the circuit is a differential circuit.
11. A method for constructing a circuit comprising:
forming a plurality of circuit components on a semi conductive substrate die, including:
forming at least one active component that operates on an information signal;
forming a tuning node that couples to the at least one active component;
forming a rail;
forming an Electro Static Discharge (ESD) protection inductor that communicatively couples between the tuning node and the rail, the ESD protection inductor providing ESD protection prior to packaging of the semi conductive substrate die; and
forming a chip pad that couples to the tuning node.
12. The method of claim 11 , wherein the ESD protection inductor has a substantially lower Quality (Q) than the bond wire.
13. The method of claim 11 , further comprising packaging the semi conductive substrate die, including:
mounting the semi conductive substrate die into a package;
coupling a bond wire between the chip pad and a package pad, the bond wire serving as a tuning inductor for the circuit.
14. The method of claim 13 :
wherein the rail is a voltage supply rail; and
further comprising coupling the chip pad to a package voltage supply.
15. The method of claim 13 :
wherein the rail is a ground rail; and
further comprising coupling the chip pad to a package ground.
16. The circuit of claim 13 , wherein coupling the bond wire between the chip pad and the package ground comprises coupling the bond wire to a down bond rail of the package that couples to a heat slug upon which the semi conductive die is mounted.
17. The method of claim 11 , wherein the at least one active component is operable to receive a voltage signal and to produce a current signal.
18. The method of claim 11 , wherein forming the ESD protection inductor comprises forming a spiral inductor in a plurality of metal layers upon the semi conductive substrate die.
19. The method of claim 11 , wherein the information signal is an RF signal.
20. The method of claim 19 , wherein the circuit is an RF power amplifier.